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Update A64 ATF patches

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This commit is contained in:
zador-blood-stained 2017-10-14 21:49:08 +03:00
parent ff09893542
commit 524fffa2ef
8 changed files with 79 additions and 26 deletions
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13
patch/atf/atf-sun50iw1/board_pine64so/set-lpddr3-dram-voltage.patch
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@ -1,13 +0,0 @@
diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
index 5aa63fe4..95bef606 100644
--- a/plat/sun50iw1p1/sunxi_power.c
+++ b/plat/sun50iw1p1/sunxi_power.c
@@ -126,7 +126,7 @@ static int axp803_initial_setup(void)
ret = sunxi_rsb_read(0x24); /* read DCDC5 register */
if ((ret & 0x7f) == 0x26) { /* check for 1.24V value */
NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.36V\n");
- sunxi_rsb_write(0x24, 0x2c);
+ sunxi_rsb_write(0x24, 0x25);
}
sunxi_rsb_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */

13
patch/atf/atf-sun50iw1/board_pinebook-a64/set-lpddr3-dram-voltage.patch
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@ -1,13 +0,0 @@
diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
index 5aa63fe4..95bef606 100644
--- a/plat/sun50iw1p1/sunxi_power.c
+++ b/plat/sun50iw1p1/sunxi_power.c
@@ -126,7 +126,7 @@ static int axp803_initial_setup(void)
ret = sunxi_rsb_read(0x24); /* read DCDC5 register */
if ((ret & 0x7f) == 0x26) { /* check for 1.24V value */
NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.36V\n");
- sunxi_rsb_write(0x24, 0x2c);
+ sunxi_rsb_write(0x24, 0x25);
}
sunxi_rsb_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */

0
patch/atf/atf-sun50iw1/add-SRAM-mapping-for-SCPI.patch → patch/atf/atf-sunxi64/add-SRAM-mapping-for-SCPI.patch
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19
patch/atf/atf-sunxi64/board_pine64so/set-lpddr3-dram-voltage.patch Normal file
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@ -0,0 +1,19 @@
diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
index db79047..fb1b108 100644
--- a/plat/sun50iw1p1/sunxi_power.c
+++ b/plat/sun50iw1p1/sunxi_power.c
@@ -261,12 +261,8 @@ static int pmic_setup(void)
* changes. This should be further confined once we are able to
* reliably detect a Pine64 board.
*/
- ret = sunxi_pmic_read(0x24); /* read DCDC5 register */
- if ((ret & 0x7f) == 0x26) { /* check for 1.24V value */
- NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.36V\n");
- sunxi_pmic_write(0x24, 0x2c);
- }
-
+ sunxi_pmic_write(0x24, 0x25);
+
sunxi_pmic_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
sunxi_pmic_write(0x16, 0x12); /* DLDO2 = VCC2V5_EDP voltage = 2.5V */

19
patch/atf/atf-sunxi64/board_pinebook-a64/set-lpddr3-dram-voltage.patch Normal file
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@ -0,0 +1,19 @@
diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
index db79047..fb1b108 100644
--- a/plat/sun50iw1p1/sunxi_power.c
+++ b/plat/sun50iw1p1/sunxi_power.c
@@ -261,12 +261,8 @@ static int pmic_setup(void)
* changes. This should be further confined once we are able to
* reliably detect a Pine64 board.
*/
- ret = sunxi_pmic_read(0x24); /* read DCDC5 register */
- if ((ret & 0x7f) == 0x26) { /* check for 1.24V value */
- NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.36V\n");
- sunxi_pmic_write(0x24, 0x2c);
- }
-
+ sunxi_pmic_write(0x24, 0x25);
+
sunxi_pmic_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
sunxi_pmic_write(0x16, 0x12); /* DLDO2 = VCC2V5_EDP voltage = 2.5V */

0
patch/atf/atf-sun50iw1/enable-a53-errata-workaround.patch → patch/atf/atf-sunxi64/enable-a53-errata-workaround.patch
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41
patch/atf/atf-sunxi64/enable-additional-regulators.patch Normal file
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@ -0,0 +1,41 @@
diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
index 0c2487e..db79047 100644
--- a/plat/sun50iw1p1/sunxi_power.c
+++ b/plat/sun50iw1p1/sunxi_power.c
@@ -217,6 +217,9 @@ static int pmic_setup(void)
{
int ret;
+ /* Set DCDC2/CPU voltage to 1.1V */
+ sunxi_pmic_write(0x21, 60);
+
ret = sunxi_pmic_read(0x20);
if (ret != 0x0e && ret != 0x11) {
int voltage = (ret & 0x1f) * 10 + 16;
@@ -242,9 +245,9 @@ static int pmic_setup(void)
return -3;
}
- if ((ret & 0xc9) != 0xc9) {
+ if ((ret & 0xd9) != 0xd9) {
/* Enable DC1SW to power PHY, DLDO4 for WiFi and DLDO1 for HDMI */
- ret = sunxi_pmic_write(0x12, ret | 0xc8);
+ ret = sunxi_pmic_write(0x12, ret | 0xd8);
if (ret < 0) {
NOTICE("PMIC: error %d enabling DC1SW/DLDO4/DLDO1\n", ret);
return -4;
@@ -266,6 +269,14 @@ static int pmic_setup(void)
sunxi_pmic_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
+ sunxi_pmic_write(0x16, 0x12); /* DLDO2 = VCC2V5_EDP voltage = 2.5V */
+ sunxi_pmic_write(0x1c, 0xa); /* FLDO1 = VCC1V2_EDP voltage = 1.2V */
+ sunxi_pmic_write(0x91, 0x1a); /* GPIO0LDO voltage = 3.3V */
+ sunxi_pmic_write(0x90, 0x3); /* Enable GPIO0LDO */
+ ret = sunxi_pmic_read(0x13);
+ /* Enable FLDO1 to power up eDP bridge */
+ ret = sunxi_pmic_write(0x13, ret | 0x4);
+
return 0;
}

0
patch/atf/atf-sun50iw1/set-rsb-to-nonsec.patch → patch/atf/atf-sunxi64/set-rsb-to-nonsec.patch
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