Making Rabbbit happy - drop .orig garbage from the patches
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aa2e963721
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@ -4,9 +4,7 @@ Date: Sun, 21 Dec 2025 11:05:52
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Subject: arm64: allwinner: a523: Support SPI controllers
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Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
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arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
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arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig
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arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
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arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig
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drivers/spi/spi-sun6i.c
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https://patchwork.kernel.org/project/linux-arm-kernel/cover/20251221110513.1850535-1-wens@kernel.org/
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@ -15,11 +13,9 @@ Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
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---
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Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 4 +
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arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 94 ++++++
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arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig | 154 ++++++++++
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arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 15 +
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arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig | 5 +-
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drivers/spi/spi-sun6i.c | 11 +-
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6 files changed, 278 insertions(+), 5 deletions(-)
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4 files changed, 278 insertions(+), 5 deletions(-)
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diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
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index 3b47b68b92cb..1b91d1566c95 100644
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@ -182,259 +178,6 @@ index d42e3d97fc7d..3bc042be5ab5 100644
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reg = <0x7102000 0x200>;
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clocks = <&osc24M>,
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<&rtc CLK_OSC32K>,
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diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig
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index 42dab01e3f56..d42e3d97fc7d 100644
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--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig
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+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig
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@@ -9,10 +9,11 @@
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#include <dt-bindings/reset/sun55i-a523-ccu.h>
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#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
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#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
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#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h>
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#include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h>
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+#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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@@ -24,59 +25,67 @@
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x000>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x100>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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cpu2: cpu@200 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x200>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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cpu3: cpu@300 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x300>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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cpu4: cpu@400 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x400>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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cpu5: cpu@500 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x500>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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cpu6: cpu@600 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x600>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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cpu7: cpu@700 {
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compatible = "arm,cortex-a55";
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device_type = "cpu";
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reg = <0x700>;
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enable-method = "psci";
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+ #cooling-cells = <2>;
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};
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};
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osc24M: osc24M-clk {
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#clock-cells = <0>;
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@@ -469,16 +478,50 @@
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dma-requests = <54>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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+ ths1: thermal-sensor@2009400 {
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+ compatible = "allwinner,sun55i-a523-ths1";
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+ reg = <0x02009400 0x400>;
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+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>;
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+ clock-names = "bus", "gpadc";
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+ resets = <&ccu RST_BUS_THS>;
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+ nvmem-cells = <&ths_calibration0>, <&ths_calibration1>;
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+ nvmem-cell-names = "calibration",
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+ "calibration-second-part";
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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+ ths0: thermal-sensor@200a000 {
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+ compatible = "allwinner,sun55i-a523-ths0";
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+ reg = <0x0200a000 0x400>;
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+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>;
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+ clock-names = "bus", "gpadc";
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+ resets = <&ccu RST_BUS_THS>;
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+ nvmem-cells = <&ths_calibration0>, <&ths_calibration1>;
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+ nvmem-cell-names = "calibration",
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+ "calibration-second-part";
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+ #thermal-sensor-cells = <0>;
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+ };
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+
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sid: efuse@3006000 {
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compatible = "allwinner,sun55i-a523-sid",
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"allwinner,sun50i-a64-sid";
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reg = <0x03006000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ ths_calibration0: ths-calibration0@38 {
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+ reg = <0x38 0x8>;
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+ };
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+
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+ ths_calibration1: ths-calibration1@44 {
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+ reg = <0x44 0x8>;
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+ };
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};
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gic: interrupt-controller@3400000 {
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compatible = "arm,gic-v3";
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#address-cells = <1>;
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@@ -934,6 +977,117 @@
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clock-names = "bus", "core", "reg";
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resets = <&mcu_ccu RST_BUS_MCU_NPU>;
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power-domains = <&ppu PD_NPU>;
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};
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};
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+
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+ thermal-zones {
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+ cpu0_thermal: cpu0-thermal {
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+ polling-delay-passive = <100>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&ths1 1>;
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+ sustainable-power = <1200>;
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+
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+ trips {
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+ cpu0_threshold: cpu-trip-0 {
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+ temperature = <70000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ cpu0_target: cpu-trip-1 {
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+ temperature = <90000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ cpu0_critical: cpu-trip-2 {
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+ temperature = <110000>;
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+ type = "critical";
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+ hysteresis = <0>;
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&cpu0_target>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+ };
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+
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+ cpu4_thermal: cpu4-thermal {
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+ polling-delay-passive = <100>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&ths1 0>;
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+ sustainable-power = <1600>;
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+
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+ trips {
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+ cpu4_threshold: cpu-trip-0 {
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+ temperature = <70000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ cpu4_target: cpu-trip-1 {
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+ temperature = <90000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ cpu4_critical: cpu-trip-2 {
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+ temperature = <110000>;
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+ type = "critical";
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+ hysteresis = <0>;
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&cpu4_target>;
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+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+ };
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+
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+ gpu-thermal {
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+ polling-delay-passive = <100>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&ths1 2>;
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+ sustainable-power = <2400>;
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+
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+ gpu-trips {
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+ gpu_temp_threshold: gpu-trip-0 {
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+ temperature = <60000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ gpu_temp_target: gpu-trip-1 {
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+ temperature = <90000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ gpu_temp_critical: gpu-trip-2 {
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+ temperature = <110000>;
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+ type = "critical";
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+ hysteresis = <0>;
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+ };
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+ };
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+ };
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+
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+ ddr-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths0>;
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+
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+ trips {
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+ ddr_temp_critical: ddr-trip-0 {
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+ temperature = <110000>;
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+ type = "critical";
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+ hysteresis = <0>;
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+ };
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+ };
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+ };
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+ };
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};
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diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
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index dcbf027a04ef..84a41becc15d 100644
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--- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
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@ -465,28 +208,6 @@ index dcbf027a04ef..84a41becc15d 100644
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pinctrl-0 = <&uart0_pb_pins>;
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status = "okay";
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};
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diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig
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index 9e6b21cf293e..dcbf027a04ef 100644
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--- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig
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+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig
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@@ -366,13 +366,16 @@
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reg_dcdc1_323: dcdc1 {
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regulator-always-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1150000>;
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regulator-name = "vdd-cpub";
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+ x-powers,polyphased = <®_dcdc2_323>;
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};
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- /* DCDC2 is polyphased with DCDC1 */
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+ reg_dcdc2_323: dcdc2 {
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+ /* dual-phased with DCDC1 */
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+ };
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/* Some RISC-V management core related voltage */
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reg_dcdc3_323: dcdc3 {
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regulator-always-on;
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regulator-min-microvolt = <900000>;
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diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
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index 871dfd3e77be..d1de6c99e762 100644
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--- a/drivers/spi/spi-sun6i.c
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