diff --git a/patch/kernel/archive/sunxi-6.18/patches.backports/30-allwinner-a523-support-spi-controllers.patch b/patch/kernel/archive/sunxi-6.18/patches.backports/30-allwinner-a523-support-spi-controllers.patch index 9ef63c23b9..54b1b8fbf7 100644 --- a/patch/kernel/archive/sunxi-6.18/patches.backports/30-allwinner-a523-support-spi-controllers.patch +++ b/patch/kernel/archive/sunxi-6.18/patches.backports/30-allwinner-a523-support-spi-controllers.patch @@ -4,9 +4,7 @@ Date: Sun, 21 Dec 2025 11:05:52 Subject: arm64: allwinner: a523: Support SPI controllers Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi - arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts - arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig drivers/spi/spi-sun6i.c https://patchwork.kernel.org/project/linux-arm-kernel/cover/20251221110513.1850535-1-wens@kernel.org/ @@ -15,11 +13,9 @@ Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 4 + arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 94 ++++++ - arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig | 154 ++++++++++ arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 15 + - arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig | 5 +- drivers/spi/spi-sun6i.c | 11 +- - 6 files changed, 278 insertions(+), 5 deletions(-) + 4 files changed, 278 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 3b47b68b92cb..1b91d1566c95 100644 @@ -182,259 +178,6 @@ index d42e3d97fc7d..3bc042be5ab5 100644 reg = <0x7102000 0x200>; clocks = <&osc24M>, <&rtc CLK_OSC32K>, -diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig -index 42dab01e3f56..d42e3d97fc7d 100644 ---- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig -+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi.orig -@@ -9,10 +9,11 @@ - #include - #include - #include - #include - #include -+#include - - / { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; -@@ -24,59 +25,67 @@ - cpu0: cpu@0 { - compatible = "arm,cortex-a55"; - device_type = "cpu"; - reg = <0x000>; - enable-method = "psci"; -+ #cooling-cells = <2>; - }; - - cpu1: cpu@100 { - compatible = "arm,cortex-a55"; - device_type = "cpu"; - reg = <0x100>; - enable-method = "psci"; -+ #cooling-cells = <2>; - }; - - cpu2: cpu@200 { - compatible = "arm,cortex-a55"; - device_type = "cpu"; - reg = <0x200>; - enable-method = "psci"; -+ #cooling-cells = <2>; - }; - - cpu3: cpu@300 { - compatible = "arm,cortex-a55"; - device_type = "cpu"; - reg = <0x300>; - enable-method = "psci"; -+ #cooling-cells = <2>; - }; - - cpu4: cpu@400 { - compatible = "arm,cortex-a55"; - device_type = "cpu"; - reg = <0x400>; - enable-method = "psci"; -+ #cooling-cells = <2>; - }; - - cpu5: cpu@500 { - compatible = "arm,cortex-a55"; - device_type = "cpu"; - reg = <0x500>; - enable-method = "psci"; -+ #cooling-cells = <2>; - }; - - cpu6: cpu@600 { - compatible = "arm,cortex-a55"; - device_type = "cpu"; - reg = <0x600>; - enable-method = "psci"; -+ #cooling-cells = <2>; - }; - - cpu7: cpu@700 { - compatible = "arm,cortex-a55"; - device_type = "cpu"; - reg = <0x700>; - enable-method = "psci"; -+ #cooling-cells = <2>; - }; - }; - - osc24M: osc24M-clk { - #clock-cells = <0>; -@@ -469,16 +478,50 @@ - dma-requests = <54>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - -+ ths1: thermal-sensor@2009400 { -+ compatible = "allwinner,sun55i-a523-ths1"; -+ reg = <0x02009400 0x400>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; -+ clock-names = "bus", "gpadc"; -+ resets = <&ccu RST_BUS_THS>; -+ nvmem-cells = <&ths_calibration0>, <&ths_calibration1>; -+ nvmem-cell-names = "calibration", -+ "calibration-second-part"; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ ths0: thermal-sensor@200a000 { -+ compatible = "allwinner,sun55i-a523-ths0"; -+ reg = <0x0200a000 0x400>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>; -+ clock-names = "bus", "gpadc"; -+ resets = <&ccu RST_BUS_THS>; -+ nvmem-cells = <&ths_calibration0>, <&ths_calibration1>; -+ nvmem-cell-names = "calibration", -+ "calibration-second-part"; -+ #thermal-sensor-cells = <0>; -+ }; -+ - sid: efuse@3006000 { - compatible = "allwinner,sun55i-a523-sid", - "allwinner,sun50i-a64-sid"; - reg = <0x03006000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ ths_calibration0: ths-calibration0@38 { -+ reg = <0x38 0x8>; -+ }; -+ -+ ths_calibration1: ths-calibration1@44 { -+ reg = <0x44 0x8>; -+ }; - }; - - gic: interrupt-controller@3400000 { - compatible = "arm,gic-v3"; - #address-cells = <1>; -@@ -934,6 +977,117 @@ - clock-names = "bus", "core", "reg"; - resets = <&mcu_ccu RST_BUS_MCU_NPU>; - power-domains = <&ppu PD_NPU>; - }; - }; -+ -+ thermal-zones { -+ cpu0_thermal: cpu0-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <1000>; -+ thermal-sensors = <&ths1 1>; -+ sustainable-power = <1200>; -+ -+ trips { -+ cpu0_threshold: cpu-trip-0 { -+ temperature = <70000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ cpu0_target: cpu-trip-1 { -+ temperature = <90000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ cpu0_critical: cpu-trip-2 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu0_target>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ cpu4_thermal: cpu4-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <1000>; -+ thermal-sensors = <&ths1 0>; -+ sustainable-power = <1600>; -+ -+ trips { -+ cpu4_threshold: cpu-trip-0 { -+ temperature = <70000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ cpu4_target: cpu-trip-1 { -+ temperature = <90000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ cpu4_critical: cpu-trip-2 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu4_target>; -+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ gpu-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <1000>; -+ thermal-sensors = <&ths1 2>; -+ sustainable-power = <2400>; -+ -+ gpu-trips { -+ gpu_temp_threshold: gpu-trip-0 { -+ temperature = <60000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ gpu_temp_target: gpu-trip-1 { -+ temperature = <90000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ gpu_temp_critical: gpu-trip-2 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ -+ ddr-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths0>; -+ -+ trips { -+ ddr_temp_critical: ddr-trip-0 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ }; - }; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index dcbf027a04ef..84a41becc15d 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -465,28 +208,6 @@ index dcbf027a04ef..84a41becc15d 100644 pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; -diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig -index 9e6b21cf293e..dcbf027a04ef 100644 ---- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig -+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts.orig -@@ -366,13 +366,16 @@ - reg_dcdc1_323: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1150000>; - regulator-name = "vdd-cpub"; -+ x-powers,polyphased = <®_dcdc2_323>; - }; - -- /* DCDC2 is polyphased with DCDC1 */ -+ reg_dcdc2_323: dcdc2 { -+ /* dual-phased with DCDC1 */ -+ }; - - /* Some RISC-V management core related voltage */ - reg_dcdc3_323: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 871dfd3e77be..d1de6c99e762 100644 --- a/drivers/spi/spi-sun6i.c