594 lines
16 KiB
Diff
594 lines
16 KiB
Diff
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
|
@@ -251,16 +251,131 @@
|
|
};
|
|
};
|
|
|
|
+ sata1: sata@fc400000 {
|
|
+ compatible = "snps,dwc-ahci";
|
|
+ reg = <0 0xfc400000 0 0x1000>;
|
|
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
|
|
+ <&cru CLK_SATA1_RXOOB>;
|
|
+ clock-names = "sata", "pmalive", "rxoob";
|
|
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hostc";
|
|
+ phys = <&combphy1 PHY_TYPE_SATA>;
|
|
+ phy-names = "sata-phy";
|
|
+ ports-implemented = <0x1>;
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sata2: sata@fc800000 {
|
|
+ compatible = "snps,dwc-ahci";
|
|
+ reg = <0 0xfc800000 0 0x1000>;
|
|
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
|
|
+ <&cru CLK_SATA2_RXOOB>;
|
|
+ clock-names = "sata", "pmalive", "rxoob";
|
|
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hostc";
|
|
+ phys = <&combphy2 PHY_TYPE_SATA>;
|
|
+ phy-names = "sata-phy";
|
|
+ ports-implemented = <0x1>;
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host0_xhci: usb@fcc00000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0xfcc00000 0x0 0x400000>;
|
|
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
|
|
+ <&cru ACLK_USB3OTG0>;
|
|
+ clock-names = "ref_clk", "suspend_clk",
|
|
+ "bus_clk";
|
|
+ dr_mode = "host";
|
|
+ phy_type = "utmi_wide";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ resets = <&cru SRST_USB3OTG0>;
|
|
+ snps,dis_u2_susphy_quirk;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host1_xhci: usb@fd000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0xfd000000 0x0 0x400000>;
|
|
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
|
|
+ <&cru ACLK_USB3OTG1>;
|
|
+ clock-names = "ref_clk", "suspend_clk",
|
|
+ "bus_clk";
|
|
+ dr_mode = "host";
|
|
+ phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ phy_type = "utmi_wide";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ resets = <&cru SRST_USB3OTG1>;
|
|
+ snps,dis_u2_susphy_quirk;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
gic: interrupt-controller@fd400000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
|
<0x0 0xfd460000 0 0x80000>; /* GICR */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
+ ranges;
|
|
#interrupt-cells = <3>;
|
|
- mbi-alias = <0x0 0xfd410000>;
|
|
- mbi-ranges = <296 24>;
|
|
- msi-controller;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ its: interrupt-controller@fd440000 {
|
|
+ compatible = "arm,gic-v3-its";
|
|
+ reg = <0x0 0xfd440000 0x0 0x20000>;
|
|
+ msi-controller;
|
|
+ #msi-cells = <1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb_host0_ehci: usb@fd800000 {
|
|
+ compatible = "generic-ehci";
|
|
+ reg = <0x0 0xfd800000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
|
+ <&cru PCLK_USB>;
|
|
+ phys = <&usb2phy1_otg>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host0_ohci: usb@fd840000 {
|
|
+ compatible = "generic-ohci";
|
|
+ reg = <0x0 0xfd840000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
|
+ <&cru PCLK_USB>;
|
|
+ phys = <&usb2phy1_otg>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host1_ehci: usb@fd880000 {
|
|
+ compatible = "generic-ehci";
|
|
+ reg = <0x0 0xfd880000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
|
+ <&cru PCLK_USB>;
|
|
+ phys = <&usb2phy1_host>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host1_ohci: usb@fd8c0000 {
|
|
+ compatible = "generic-ohci";
|
|
+ reg = <0x0 0xfd8c0000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
|
+ <&cru PCLK_USB>;
|
|
+ phys = <&usb2phy1_host>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
};
|
|
|
|
pmugrf: syscon@fdc20000 {
|
|
@@ -274,7 +389,6 @@
|
|
};
|
|
|
|
pipegrf: syscon@fdc50000 {
|
|
- compatible = "rockchip,rk3568-pipe-grf", "syscon";
|
|
reg = <0x0 0xfdc50000 0x0 0x1000>;
|
|
};
|
|
|
|
@@ -291,6 +405,16 @@
|
|
pipe_phy_grf2: syscon@fdc90000 {
|
|
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
|
|
reg = <0x0 0xfdc90000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ usb2phy0_grf: syscon@fdca0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdca0000 0x0 0x8000>;
|
|
+ };
|
|
+
|
|
+ usb2phy1_grf: syscon@fdca8000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdca8000 0x0 0x8000>;
|
|
};
|
|
|
|
pmucru: clock-controller@fdd00000 {
|
|
@@ -330,6 +454,7 @@
|
|
clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 0>, <&dmac0 1>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -495,6 +620,28 @@
|
|
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
|
power-domains = <&power RK3568_PD_VPU>;
|
|
#iommu-cells = <0>;
|
|
+ };
|
|
+
|
|
+ ebc: ebc@fdec0000 {
|
|
+ compatible = "rockchip,rk3568-ebc-tcon";
|
|
+ reg = <0x0 0xfdec0000 0x0 0x5000>;
|
|
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
|
|
+ clock-names = "hclk", "dclk";
|
|
+ pinctrl-0 = <&ebc_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ power-domains = <&power RK3568_PD_RGA>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ eink: eink@fdf00000 {
|
|
+ compatible = "rockchip,rk3568-eink-tcon";
|
|
+ reg = <0x0 0xfdf00000 0x0 0x74>;
|
|
+ clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
|
|
+ clock-names = "pclk", "hclk";
|
|
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
};
|
|
|
|
sdmmc2: mmc@fe000000 {
|
|
@@ -604,6 +751,62 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ dsi0: dsi@fe060000 {
|
|
+ compatible = "rockchip,rk3568-mipi-dsi";
|
|
+ reg = <0x0 0xfe060000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>;
|
|
+ clock-names = "pclk", "hclk", "hs_clk";
|
|
+ phys = <&video_phy0>;
|
|
+ phy-names = "dphy";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ resets = <&cru SRST_P_DSITX_0>;
|
|
+ reset-names = "apb";
|
|
+ rockchip,grf = <&grf>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dsi0_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dsi1: dsi@fe070000 {
|
|
+ compatible = "rockchip,rk3568-mipi-dsi";
|
|
+ reg = <0x0 0xfe070000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>;
|
|
+ clock-names = "pclk", "hclk", "hs_clk";
|
|
+ phys = <&video_phy1>;
|
|
+ phy-names = "dphy";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ resets = <&cru SRST_P_DSITX_1>;
|
|
+ reset-names = "apb";
|
|
+ rockchip,grf = <&grf>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dsi1_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
hdmi: hdmi@fe0a0000 {
|
|
compatible = "rockchip,rk3568-dw-hdmi";
|
|
reg = <0x0 0xfe0a0000 0x0 0x20000>;
|
|
@@ -628,10 +831,14 @@
|
|
|
|
hdmi_in: port@0 {
|
|
reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
};
|
|
|
|
hdmi_out: port@1 {
|
|
reg = <1>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
@@ -754,6 +961,61 @@
|
|
qos_vop_m1: qos@fe1a8100 {
|
|
compatible = "rockchip,rk3568-qos", "syscon";
|
|
reg = <0x0 0xfe1a8100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ pcie2x1: pcie@fe260000 {
|
|
+ compatible = "rockchip,rk3568-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ bus-range = <0x0 0xf>;
|
|
+ assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
|
|
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
|
|
+ <&cru CLK_PCIE20_AUX_NDFT>;
|
|
+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
|
|
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
|
|
+ <&cru CLK_PCIE20_AUX_NDFT>;
|
|
+ clock-names = "aclk_mst", "aclk_slv",
|
|
+ "aclk_dbi", "pclk", "aux";
|
|
+ device_type = "pci";
|
|
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "sys", "pmc", "msi", "legacy", "err";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
|
+ <0 0 0 2 &pcie_intc 1>,
|
|
+ <0 0 0 3 &pcie_intc 2>,
|
|
+ <0 0 0 4 &pcie_intc 3>;
|
|
+ linux,pci-domain = <0>;
|
|
+ num-ib-windows = <6>;
|
|
+ num-ob-windows = <2>;
|
|
+ max-link-speed = <2>;
|
|
+ msi-map = <0x0 &its 0x0 0x1000>;
|
|
+ num-lanes = <1>;
|
|
+ phys = <&combphy2 PHY_TYPE_PCIE>;
|
|
+ phy-names = "pcie-phy";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ reg = <0x3 0xc0000000 0x0 0x00400000>,
|
|
+ <0x0 0xfe260000 0x0 0x00010000>,
|
|
+ <0x3 0x00000000 0x0 0x01000000>;
|
|
+ ranges = <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000
|
|
+ 0x02000000 0x0 0x02000000 0x3 0x02000000 0x0 0x3e000000>;
|
|
+ reg-names = "dbi", "apb", "config";
|
|
+ resets = <&cru SRST_PCIE20_POWERUP>;
|
|
+ reset-names = "pipe";
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie_intc: legacy-interrupt-controller {
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-controller;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+
|
|
};
|
|
|
|
sdmmc0: mmc@fe2b0000 {
|
|
@@ -781,6 +1043,19 @@
|
|
max-frequency = <150000000>;
|
|
resets = <&cru SRST_SDMMC1>;
|
|
reset-names = "reset";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sfc: spi@fe300000 {
|
|
+ compatible = "rockchip,sfc";
|
|
+ reg = <0x0 0xfe300000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
|
+ clock-names = "clk_sfc", "hclk_sfc";
|
|
+ assigned-clocks = <&cru SCLK_SFC>;
|
|
+ assigned-clock-rates = <100000000>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -853,6 +1128,43 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ i2s2_2ch: i2s@fe420000 {
|
|
+ compatible = "rockchip,rk3568-i2s-tdm";
|
|
+ reg = <0x0 0xfe420000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
|
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
+ dmas = <&dmac1 4>, <&dmac1 5>;
|
|
+ dma-names = "tx", "rx";
|
|
+ rockchip,cru = <&cru>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ pinctrl-0 = <&i2s2m0_sclktx
|
|
+ &i2s2m0_lrcktx
|
|
+ &i2s2m0_sdi
|
|
+ &i2s2m0_sdo>;
|
|
+ pinctrl-names = "default";
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pdm: pdm@fe440000 {
|
|
+ compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
|
|
+ reg = <0x0 0xfe440000 0x0 0x1000>;
|
|
+ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
|
|
+ clock-names = "pdm_clk", "pdm_hclk";
|
|
+ dmas = <&dmac1 9>;
|
|
+ dma-names = "rx";
|
|
+ pinctrl-0 = <&pdmm0_clk
|
|
+ &pdmm0_clk1
|
|
+ &pdmm0_sdi0
|
|
+ &pdmm0_sdi1
|
|
+ &pdmm0_sdi2
|
|
+ &pdmm0_sdi3>;
|
|
+ pinctrl-names = "default";
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
dmac0: dma-controller@fe530000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0xfe530000 0x0 0x4000>;
|
|
@@ -1015,6 +1327,7 @@
|
|
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 2>, <&dmac0 3>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart1m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -1029,6 +1342,7 @@
|
|
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 4>, <&dmac0 5>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart2m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -1043,6 +1357,7 @@
|
|
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 6>, <&dmac0 7>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart3m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -1057,6 +1372,7 @@
|
|
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 8>, <&dmac0 9>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart4m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -1071,6 +1387,7 @@
|
|
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 10>, <&dmac0 11>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart5m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -1085,6 +1402,7 @@
|
|
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 12>, <&dmac0 13>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart6m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -1099,6 +1417,7 @@
|
|
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 14>, <&dmac0 15>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart7m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -1113,6 +1432,7 @@
|
|
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 16>, <&dmac0 17>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart8m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
@@ -1127,10 +1447,41 @@
|
|
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
dmas = <&dmac0 18>, <&dmac0 19>;
|
|
+ dma-names = "tx", "rx";
|
|
pinctrl-0 = <&uart9m0_xfer>;
|
|
pinctrl-names = "default";
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ video_phy0: video-phy@fe850000 {
|
|
+ compatible = "rockchip,rk3568-video-phy";
|
|
+ reg = <0x0 0xfe850000 0x0 0x10000>,
|
|
+ <0x0 0xfe060000 0x0 0x10000>;
|
|
+ clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
|
|
+ <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
|
|
+ clock-names = "ref", "pclk_phy", "pclk_host";
|
|
+ #clock-cells = <0>;
|
|
+ resets = <&cru SRST_P_MIPIDSIPHY0>;
|
|
+ reset-names = "rst";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ video_phy1: video-phy@fe860000 {
|
|
+ compatible = "rockchip,rk3568-video-phy";
|
|
+ reg = <0x0 0xfe860000 0x0 0x10000>,
|
|
+ <0x0 0xfe070000 0x0 0x10000>;
|
|
+ clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
|
|
+ <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
|
|
+ clock-names = "ref", "pclk_phy", "pclk_host";
|
|
+ #clock-cells = <0>;
|
|
+ resets = <&cru SRST_P_MIPIDSIPHY1>;
|
|
+ reset-names = "rst";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ #phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1370,6 +1721,82 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+// combphy1: phy@fe830000 {
|
|
+// compatible = "rockchip,rk3568-naneng-combphy";
|
|
+// reg = <0x0 0xfe830000 0x0 0x100>;
|
|
+// clocks = <&pmucru CLK_PCIEPHY1_REF>,
|
|
+// <&cru PCLK_PIPEPHY1>,
|
|
+// <&cru PCLK_PIPE>;
|
|
+// clock-names = "ref", "apb", "pipe";
|
|
+// assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
|
|
+// assigned-clock-rates = <100000000>;
|
|
+// resets = <&cru SRST_PIPEPHY1>;
|
|
+// rockchip,pipe-grf = <&pipegrf>;
|
|
+// rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
|
|
+// #phy-cells = <1>;
|
|
+// status = "disabled";
|
|
+// };
|
|
+
|
|
+// combphy2: phy@fe840000 {
|
|
+// compatible = "rockchip,rk3568-naneng-combphy";
|
|
+// reg = <0x0 0xfe840000 0x0 0x100>;
|
|
+// clocks = <&pmucru CLK_PCIEPHY2_REF>,
|
|
+// <&cru PCLK_PIPEPHY2>,
|
|
+// <&cru PCLK_PIPE>;
|
|
+// clock-names = "ref", "apb", "pipe";
|
|
+// assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
|
|
+// assigned-clock-rates = <100000000>;
|
|
+// resets = <&cru SRST_PIPEPHY2>;
|
|
+// rockchip,pipe-grf = <&pipegrf>;
|
|
+// rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
|
|
+// #phy-cells = <1>;
|
|
+// status = "disabled";
|
|
+// };
|
|
+
|
|
+ usb2phy0: usb2phy@fe8a0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy";
|
|
+ reg = <0x0 0xfe8a0000 0x0 0x10000>;
|
|
+ clocks = <&pmucru CLK_USBPHY0_REF>;
|
|
+ clock-names = "phyclk";
|
|
+ clock-output-names = "clk_usbphy0_480m";
|
|
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ rockchip,usbgrf = <&usb2phy0_grf>;
|
|
+ #clock-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ usb2phy0_host: host-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb2phy0_otg: otg-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2phy1: usb2phy@fe8b0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy";
|
|
+ reg = <0x0 0xfe8b0000 0x0 0x10000>;
|
|
+ clocks = <&pmucru CLK_USBPHY1_REF>;
|
|
+ clock-names = "phyclk";
|
|
+ clock-output-names = "clk_usbphy1_480m";
|
|
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ rockchip,usbgrf = <&usb2phy1_grf>;
|
|
+ #clock-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ usb2phy1_host: host-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb2phy1_otg: otg-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3568-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
|