move kernel media-current to 5.17 and media-edge to 5.18 (#3726)

config/sources/families/jetson-nano.conf

@@ -21,7 +21,7 @@ case $BRANCH in
 	;;
 
 	current)
-		KERNELBRANCH="branch:linux-5.15.y"
+		KERNELBRANCH="branch:linux-5.17.y"
 		KERNELPATCHDIR='media-'$BRANCH
 		LINUXFAMILY=media
 		LINUXCONFIG='linux-media-'$BRANCH
@@ -29,7 +29,8 @@ case $BRANCH in
 	;;
 
 	edge)
-		KERNELBRANCH="branch:linux-5.17.y"
+		KERNELSOURCE='https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git'
+		KERNELBRANCH="tag:v5.18-rc4"
 		KERNELPATCHDIR='media-'$BRANCH
 		LINUXFAMILY=media
 		LINUXCONFIG='linux-media-'$BRANCH

config/sources/families/media.conf

@@ -5,9 +5,9 @@ if [[ $BOARD == station-p2 || $BOARD == station-m2 ]]; then
 	BOOTBRANCH='branch:rk356x'
 	BOOTPATCHDIR="u-boot-media"
 elif [[ $BOARD == quartz64a ]]; then
-	BOOTSOURCE='https://gitlab.com/pgwipeout/u-boot-quartz64.git'
-	BOOTBRANCH='branch:quartz64'
-	BOOTPATCHDIR="u-boot-station-p2"
+	BOOTSOURCE='https://github.com/150balbes/u-boot-rk'
+	BOOTBRANCH='branch:rk35xx'
+	BOOTPATCHDIR="u-boot-media"
 fi
 
 case $BRANCH in
@@ -41,33 +41,19 @@ case $BRANCH in
 	;;
 
 	current)
-		if [[ $BOARD == station-p2 || $BOARD == station-m2 || $BOARD == quartz64a ]]; then
-			KERNELBRANCH="branch:linux-5.16.y"
-			KERNELPATCHDIR='media-edge'
-			LINUXFAMILY=station-p2
-			LINUXCONFIG='linux-media-edge'
-		else
-			KERNELBRANCH="branch:linux-5.15.y"
+			KERNELBRANCH="branch:linux-5.17.y"
 			KERNELPATCHDIR='media-'$BRANCH
 			LINUXFAMILY=media
 			LINUXCONFIG='linux-media-'$BRANCH
-		fi
 	;;
 
 	edge)
-		if [[ $BOARD == station-p2 || $BOARD == station-m2 || $BOARD == quartz64a ]]; then
-			SKIP_BOOTSPLASH="yes"
-			EXTRAWIFI="no"
-			KERNELBRANCH="branch:linux-5.17.y"
-			KERNELPATCHDIR='station-p2-'$BRANCH
-			LINUXFAMILY=station-p2
-			LINUXCONFIG='linux-station-p2-'$BRANCH
-		else
-			KERNELBRANCH="branch:linux-5.17.y"
+#			KERNELBRANCH="branch:linux-5.18.y"
+			KERNELSOURCE='https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git'
+			KERNELBRANCH="tag:v5.18-rc4"
 			KERNELPATCHDIR='media-'$BRANCH
 			LINUXFAMILY=media
 			LINUXCONFIG='linux-media-'$BRANCH
-		fi
 	;;
 esac
 

patch/kernel/archive/media-5.15/general-fix-rga-probe.patch

@@ -1,13 +0,0 @@
-diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
-index 6759091b1..d99ea8973 100644
---- a/drivers/media/platform/rockchip/rga/rga.c
-+++ b/drivers/media/platform/rockchip/rga/rga.c
-@@ -895,7 +895,7 @@ static int rga_probe(struct platform_device *pdev)
- 	}
- 	rga->dst_mmu_pages =
- 		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
--	if (rga->dst_mmu_pages) {
-+	if (!rga->dst_mmu_pages) {
- 		ret = -ENOMEM;
- 		goto free_src_pages;
- 	}

patch/kernel/archive/media-5.16/z-builddeb.patch

@@ -0,0 +1,79 @@
+--- a/scripts/package/builddeb
++++ b/scripts/package/builddeb
+@@ -64,25 +64,6 @@
+ 	chmod -R a+rX "$pdir"
+ 	# in case we build in a setuid/setgid directory
+ 	chmod -R ug-s "$pdir"
+-
+-	# Create preinstall and post install script to remove dtb
+-	if [ "$3" = "dtb" ]; then
+-
+-		cat >> $pdir/DEBIAN/preinst <<- EOT
+-			rm -rf /boot/dtb
+-			rm -rf /boot/dtb-$version
+-			exit 0
+-		EOT
+-
+-		cat >> $pdir/DEBIAN/postinst <<- EOT
+-			cd /boot
+-			ln -sfT dtb-$version dtb 2> /dev/null || mv dtb-$version dtb
+-			exit 0
+-		EOT
+-
+-		chmod 775 $pdir/DEBIAN/preinst
+-		chmod 775 $pdir/DEBIAN/postinst
+-	fi
+ 
+ 	# Create postinst prerm script for headers
+ 	if [ "$3" = "headers" ]; then
+@@ -187,7 +168,6 @@
+ kernel_headers_dir="debian/hdrtmp"
+ libc_headers_dir="debian/headertmp"
+ dbg_dir="debian/dbgtmp"
+-dtb_dir="debian/dtbtmp"
+ packagename=linux-image-"$BRANCH$LOCALVERSION"
+ kernel_headers_packagename=linux-headers-"$BRANCH$LOCALVERSION"
+ dtb_packagename=linux-dtb-"$BRANCH$LOCALVERSION"
+@@ -225,11 +205,9 @@
+ BUILD_DEBUG=$(if_enabled_echo CONFIG_DEBUG_INFO Yes)
+ 
+ # Setup the directory structure
+-rm -rf "$tmpdir" "$dbg_dir" "$dtb_dir" debian/files
++rm -rf "$tmpdir" "$dbg_dir" debian/files
+ mkdir -m 755 -p "$tmpdir/DEBIAN"
+ mkdir -p "$tmpdir/lib" "$tmpdir/boot"
+-mkdir -m 755 -p "$dtb_dir/DEBIAN"
+-mkdir -p "$dtb_dir/boot/dtb-$version" "$dtb_dir/usr/share/doc/$dtb_packagename"
+ mkdir -m 755 -p "$kernel_headers_dir/lib/modules/$version/"
+ mkdir -m 755 -p "$libc_headers_dir/DEBIAN"
+ 
+@@ -249,7 +227,7 @@
+ if is_enabled CONFIG_OF_EARLY_FLATTREE; then
+ 	# Only some architectures with OF support have this target
+ 	if [ -d "${srctree}/arch/$SRCARCH/boot/dts" ]; then
+-		$MAKE -f $srctree/Makefile INSTALL_DTBS_PATH="$tmpdir/usr/lib/linux-image-$version" dtbs_install
++		$MAKE -f $srctree/Makefile INSTALL_DTBS_PATH="$tmpdir/boot/dtb/" dtbs_install
+ 	fi
+ fi
+ 
+@@ -346,6 +324,7 @@
+ 			rm -f /boot/System.map* /boot/config* /boot/vmlinuz* /boot/$image_name /boot/uImage
+ 		fi
+ 	}
++	if [ -d /boot/dtb ]; then rm -rf /boot/dtb; fi
+ 	mountpoint -q /boot && check_boot_dev
+ 	exit 0
+ EOT
+@@ -353,11 +332,6 @@
+ create_package "$packagename" "$tmpdir"
+ 
+ if [ "$ARCH" != "um" ]; then
+-
+-	if [ "$(cat debian/arch)" != "amd64" ]; then # No DTB for amd64 target
+-		create_package "$dtb_packagename" "$dtb_dir" "dtb"
+-	fi
+-
+ 	deploy_libc_headers $libc_headers_dir
+ 	create_package $libc_headers_packagename $libc_headers_dir
+ 
+

patch/kernel/archive/media-5.16/z-mkdebian.patch

@@ -0,0 +1,24 @@
+--- a/scripts/package/mkdebian
++++ b/scripts/package/mkdebian
+@@ -98,7 +98,6 @@
+ packagename=linux-image-"$BRANCH$LOCALVERSION"
+ kernel_headers_packagename=linux-headers-"$BRANCH$LOCALVERSION"
+ libc_headers_packagename=linux-libc-dev
+-dtb_packagename=linux-dtb-"$BRANCH$LOCALVERSION"
+ dbg_packagename=$packagename-dbg
+ 
+ if [ "$ARCH" = "um" ] ; then
+@@ -198,12 +197,6 @@
+  This package provides userspaces headers from the Linux kernel.  These headers
+  are used by the installed headers for GNU glibc and other system libraries.
+ Multi-Arch: same
+-
+-Package: $dtb_packagename
+-Architecture: $debarch
+-Provides: linux-dtb, linux-dtb-armbian, armbian-$BRANCH
+-Description: Armbian Linux DTB, version $version $BRANCH
+- This package contains device blobs from the Linux kernel, version $version
+ EOF
+ 
+ if is_enabled CONFIG_MODULES; then
+

patch/kernel/archive/media-5.17/05-v91-clk-rk3568.patch

@@ -0,0 +1,20 @@
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -1059,13 +1059,13 @@
+ 			RK3568_CLKGATE_CON(20), 8, GFLAGS),
+ 	GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
+ 			RK3568_CLKGATE_CON(20), 9, GFLAGS),
+-	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
++	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
+ 			RK3568_CLKGATE_CON(20), 10, GFLAGS),
+-	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
++	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ 			RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
+ 			RK3568_CLKGATE_CON(20), 11, GFLAGS),
+-	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
++	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0,
+ 			RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
+ 			RK3568_CLKGATE_CON(20), 12, GFLAGS),
+ 	GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
+

patch/kernel/archive/media-5.17/05-v91-grf.patch

@@ -26,7 +26,7 @@
  		.compatible = "rockchip,rk3399-grf",
  		.data = (void *)&rk3399_grf,
 +	}, {
-+		.compatible = "rockchip,rk3566-pipegrf",
++		.compatible = "rockchip,rk3566-pipe-grf",
 +		.data = (void *)&rk3566_pipegrf,
  	},
  	{ /* sentinel */ },

patch/kernel/archive/media-5.17/05-v95-rk3566-firefly-roc-pc.patch

@@ -2,7 +2,7 @@ new file mode 100644
 index 000000000..fac2db500
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3566-firefly-roc-pc.dts
-@@ -0,0 +1,760 @@
+@@ -0,0 +1,784 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
@@ -31,6 +31,15 @@ index 000000000..fac2db500
 +		stdout-path = "serial2:1500000n8";
 +	};
 +
++	vcc5v0_in: vcc5v0_in {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_in";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
 +	gmac1_clkin: external-gmac1-clock {
 +		compatible = "fixed-clock";
 +		clock-frequency = <125000000>;
@@ -49,59 +58,6 @@ index 000000000..fac2db500
 +		};
 +	};
 +
-+	firefly_leds: leds {
-+		compatible = "gpio-leds";
-+		power_led: power {
-+			label = "firefly:blue:power";
-+			linux,default-trigger = "ir-power-click";
-+			default-state = "on";
-+			gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&led_power>;
-+		};
-+
-+		user_led: user {
-+			label = "firefly:yellow:user";
-+			linux,default-trigger = "ir-user-click";
-+			default-state = "off";
-+			gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&led_user>;
-+		};
-+   	};
-+
-+	rk809-sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,format = "i2s";
-+		simple-audio-card,name = "Analog RK809";
-+		simple-audio-card,mclk-fs = <256>;
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&i2s1_8ch>;
-+		};
-+		simple-audio-card,codec {
-+			sound-dai = <&rk809>;
-+		};
-+	};
-+
-+	rk_headset: rk-headset {
-+		compatible = "rockchip_headset";
-+		headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&hp_det>;
-+		io-channels = <&saradc 2>;    //HP_HOOK pin
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		status = "okay";
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk809 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_enable_h>;
-+		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
-+	};
-+
 +	vcc3v3_sys: vcc3v3-sys {
 +		compatible = "regulator-fixed";
 +		regulator-name = "vcc3v3_sys";
@@ -112,16 +68,7 @@ index 000000000..fac2db500
 +		vin-supply = <&vcc5v0_sys>;
 +	};
 +
-+	vcc5v0_in: vcc5v0_in {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_in";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys {
++	vcc5v0_sys: vcc5v0_sys {
 +		compatible = "regulator-fixed";
 +		regulator-name = "vcc5v0_sys";
 +		regulator-always-on;
@@ -167,6 +114,59 @@ index 000000000..fac2db500
 +		states = <100000 0x0
 +			  3300000 0x1>;
 +	};
++
++	firefly_leds: leds {
++		compatible = "gpio-leds";
++		power_led: power {
++			label = "firefly:blue:power";
++			linux,default-trigger = "ir-power-click";
++			default-state = "on";
++			gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&led_power>;
++		};
++
++		user_led: user {
++			label = "firefly:yellow:user";
++			linux,default-trigger = "ir-user-click";
++			default-state = "off";
++			gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&led_user>;
++		};
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		status = "okay";
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk809 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
++	};
++
++	rk809-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "Analog RK809";
++		simple-audio-card,mclk-fs = <256>;
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&rk809>;
++		};
++	};
++
++	rk_headset: rk-headset {
++		compatible = "rockchip_headset";
++		headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&hp_det>;
++		io-channels = <&saradc 2>;    //HP_HOOK pin
++	};
 +};
 +
 +&combphy1 {
@@ -260,14 +260,14 @@ index 000000000..fac2db500
 +	vdd_cpu: regulator@1c {
 +		compatible = "tcs,tcs4525";
 +		reg = <0x1c>;
-+		fcs,suspend-voltage-selector = <1>;
++		vin-supply = <&vcc5v0_sys>;
 +		regulator-name = "vdd_cpu";
 +		regulator-min-microvolt = <800000>;
 +		regulator-max-microvolt = <1150000>;
 +		regulator-ramp-delay = <2300>;
-+		regulator-always-on;
++		fcs,suspend-voltage-selector = <1>;
 +		regulator-boot-on;
-+		vin-supply = <&vcc5v0_sys>;
++		regulator-always-on;
 +
 +		regulator-state-mem {
 +			regulator-off-in-suspend;
@@ -326,11 +326,11 @@ index 000000000..fac2db500
 +			};
 +
 +			vdd_gpu: DCDC_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
 +				regulator-name = "vdd_gpu";
 +				regulator-init-microvolt = <900000>;
 +				regulator-initial-mode = <0x2>;
-+				regulator-always-on;
-+				regulator-boot-on;
 +				regulator-min-microvolt = <500000>;
 +				regulator-max-microvolt = <1350000>;
 +				regulator-ramp-delay = <6001>;
@@ -365,9 +365,9 @@ index 000000000..fac2db500
 +			};
 +
 +			vdda0v9_image: LDO_REG1 {
-+				regulator-name = "vdda0v9_image";
-+				regulator-always-on;
 +				regulator-boot-on;
++				regulator-always-on;
++				regulator-name = "vdda0v9_image";
 +				regulator-min-microvolt = <900000>;
 +				regulator-max-microvolt = <900000>;
 +
@@ -402,9 +402,9 @@ index 000000000..fac2db500
 +			};
 +
 +			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
 +				regulator-always-on;
 +				regulator-boot-on;
++				regulator-name = "vccio_acodec";
 +				regulator-min-microvolt = <3300000>;
 +				regulator-max-microvolt = <3300000>;
 +
@@ -546,13 +546,9 @@ index 000000000..fac2db500
 +};
 +
 +&pinctrl {
-+	usb {
-+		vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
-+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
 +		};
 +	};
 +
@@ -577,12 +573,18 @@ index 000000000..fac2db500
 +		};
 +	};
 +
-+	sdio-pwrseq {
-+		wifi_enable_h: wifi-enable-h {
-+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++	usb {
++		vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 +		};
 +	};
 +
++
++
 +	pcie {
 +		pcie_reset_gpio: pcie-reset-gpio {
 +			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -707,37 +709,6 @@ index 000000000..fac2db500
 +	status = "okay";
 +};
 +
-+&u2phy0_host {
-+	phy-supply = <&vcc5v0_usb30_host>;
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	vbus-supply = <&vcc5v0_usb_otg>;
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	phy-supply = <&vcc5v0_usb30_host>;
-+	status = "okay";
-+};
-+
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy1 {
-+	status = "okay";
-+};
-+
-+&usbdrd30 {
-+	status = "okay";
-+};
-+
-+&usbhost30 {
-+	status = "okay";
-+};
-+
 +&usb_host0_ehci {
 +	status = "okay";
 +};
@@ -746,6 +717,59 @@ index 000000000..fac2db500
 +	status = "okay";
 +};
 +
++&usb_host0_xhci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb30_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	vbus-supply = <&vcc5v0_usb_otg>;
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc5v0_usb30_host>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	phy-supply = <&vcc5v0_usb30_host>;
++	status = "okay";
++};
++
++//&usbdrd30 {
++//	status = "okay";
++//};
++
++//&usbhost30 {
++//	status = "okay";
++//};
++
 +&vop {
 +	compatible = "rockchip,rk3568-vop";
 +	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;

patch/kernel/archive/media-5.17/05-v95-rk3566-quartz64-a.patch

@@ -0,0 +1,630 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -19,6 +19,24 @@
+ 
+ 	chosen: chosen {
+ 		stdout-path = "serial2:1500000n8";
++	};
++
++	battery_cell: battery-cell {
++		compatible = "simple-battery";
++		charge-full-design-microamp-hours = <2500000>;
++		charge-term-current-microamp = <300000>;
++		constant-charge-current-max-microamp = <2000000>;
++		constant-charge-voltage-max-microvolt = <4200000>;
++		factory-internal-resistance-micro-ohms = <180000>;
++		voltage-max-design-microvolt = <4106000>;
++		voltage-min-design-microvolt = <3625000>;
++
++		ocv-capacity-celsius = <20>;
++		ocv-capacity-table-0 =	<4106000 100>, <4071000 95>, <4018000 90>, <3975000 85>,
++					<3946000 80>, <3908000 75>, <3877000 70>, <3853000 65>,
++					<3834000 60>, <3816000 55>, <3802000 50>, <3788000 45>,
++					<3774000 40>, <3760000 35>, <3748000 30>, <3735000 25>,
++					<3718000 20>, <3697000 15>, <3685000 10>, <3625000 0>;
+ 	};
+ 
+ 	gmac1_clkin: external-gmac1-clock {
+@@ -33,6 +51,8 @@
+ 		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ 		gpio-fan,speed-map = <0    0
+ 				      4500 1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fan_en_h>;
+ 		#cooling-cells = <2>;
+ 	};
+ 
+@@ -82,24 +102,6 @@
+ 
+ 		simple-audio-card,codec {
+ 			sound-dai = <&rk817>;
+-		};
+-	};
+-
+-	spdif_dit: spdif-dit {
+-		compatible = "linux,spdif-dit";
+-		#sound-dai-cells = <0>;
+-	};
+-
+-	spdif_sound: spdif-sound {
+-		compatible = "simple-audio-card";
+-		simple-audio-card,name = "SPDIF";
+-
+-		simple-audio-card,cpu {
+-			sound-dai = <&spdif>;
+-		};
+-
+-		simple-audio-card,codec {
+-			sound-dai = <&spdif_dit>;
+ 		};
+ 	};
+ 
+@@ -112,6 +114,24 @@
+ 		post-power-on-delay-ms = <100>;
+ 		power-off-delay-us = <5000000>;
+ 		reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
++	};
++
++	spdif_dit: spdif-dit {
++		compatible = "linux,spdif-dit";
++		#sound-dai-cells = <0>;
++	};
++
++	spdif_sound: spdif-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "SPDIF";
++
++		simple-audio-card,cpu {
++			sound-dai = <&spdif>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&spdif_dit>;
++		};
+ 	};
+ 
+ 	vcc12v_dcin: vcc12v_dcin {
+@@ -147,6 +167,54 @@
+ 		vin-supply = <&vcc12v_dcin>;
+ 	};
+ 
++	/* all four ports are controlled by one gpio
++	 * the host ports are sourced from vcc5v0_usb
++	 * the otg port is sourced from vcc5v0_midu
++	 */
++	vcc5v0_usb20_host: vcc5v0_usb20_host {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb20_host_en>;
++		regulator-name = "vcc5v0_usb20_host";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++
++	vcc5v0_usb20_otg: vcc5v0_usb20_otg {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vcc5v0_usb20_otg";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dcdc_boost>;
++	};
++
++	vcc3v3_pcie_p: vcc3v3_pcie_p {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_enable_h>;
++		regulator-name = "vcc3v3_pcie_p";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_3v3>;
++	};
++
++	vcc5v0_usb20_otg: vcc5v0_usb20_otg {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vcc5v0_usb20_otg";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dcdc_boost>;
++	};
++
+ 	vcc3v3_sd: vcc3v3_sd {
+ 		compatible = "regulator-fixed";
+ 		enable-active-low;
+@@ -171,6 +239,19 @@
+ 		vin-supply = <&vbus>;
+ 	};
+ 
++	vcc_sys_ebc: vcc_sys_ebc {
++		compatible = "regulator-fixed";
++		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_sys_ebc_h>;
++		regulator-boot-on;
++		regulator-name = "vcc_sys_ebc";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_sys>;
++	};
++
+ 	/* sourced from vcc_sys, sdio module operates internally at 3.3v */
+ 	vcc_wl: vcc_wl {
+ 		compatible = "regulator-fixed";
+@@ -181,6 +262,31 @@
+ 		regulator-max-microvolt = <3300000>;
+ 		vin-supply = <&vcc_sys>;
+ 	};
++
++	vcc_lcd_en: vcc_lcd_en {
++		compatible = "regulator-fixed";
++		gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc_lcd_en_h>;
++		regulator-name = "vcc_lcd_en";
++		vin-supply = <&vcc_3v3>;
++	};
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm14 0 1000000 0>;
++		brightness-levels = <0 4 8 16 32 64 128 255>;
++		default-brightness-level = <6>;
++	};
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&combphy2 {
++	status = "okay";
+ };
+ 
+ &cpu0 {
+@@ -214,6 +320,39 @@
+ 			cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ 		};
+ 	};
++};
++
++&ebc {
++	panel,width = <1872>;
++	panel,height = <1404>;
++	panel,vir_width = <1872>;
++	panel,vir_height = <1404>;
++	panel,sdck = <33300000>;
++	panel,lsl = <11>;
++	panel,lbl = <8>;
++	panel,ldl = <234>;
++	panel,lel = <23>;
++	panel,gdck-sta = <10>;
++	panel,lgonl = <215>;
++	panel,fsl = <1>;
++	panel,fbl = <4>;
++	panel,fdl = <1404>;
++	panel,fel = <12>;
++	panel,mirror = <1>;
++	panel,panel_16bit = <1>;
++	panel,panel_color = <0>;
++	panel,width-mm = <157>;
++	panel,height-mm = <210>;
++
++	io-channels = <&ebc_pmic 0>;
++	panel-supply = <&v3p3>;
++	vcom-supply = <&vcom>;
++	vdrive-supply = <&vdrive>;
++	status = "disabled";
++};
++
++&eink {
++	status = "disabled";
+ };
+ 
+ &gmac1 {
+@@ -239,6 +378,11 @@
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
+ &hdmi {
+ 	avdd-0v9-supply = <&vdda_0v9>;
+ 	avdd-1v8-supply = <&vcc_1v8>;
+@@ -257,8 +401,7 @@
+ 	};
+ };
+ 
+-&gpu {
+-	mali-supply = <&vdd_gpu>;
++&hdmi_sound {
+ 	status = "okay";
+ };
+ 
+@@ -481,6 +624,58 @@
+ 				};
+ 			};
+ 		};
++
++		rk817_battery: battery {
++			monitored-battery = <&battery_cell>;
++			rockchip,resistor-sense-micro-ohms = <10000>;
++			rockchip,sleep-enter-current-microamp = <300000>;
++			rockchip,sleep-filter-current-microamp = <100000>;
++		};
++	};
++};
++
++&i2c1 {
++	status = "okay";
++
++	ebc_pmic: pmic@68 {
++		compatible = "ti,tps65185";
++		reg = <0x68>;
++		interrupt-parent = <&gpio4>;
++		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++		#io-channel-cells = <1>;
++		pinctrl-0 = <&ebc_pmic_pins>;
++		pinctrl-names = "default";
++		powerup-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
++		pwr_good-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
++		vcom_ctrl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
++		vin-supply = <&vcc_sys_ebc>;
++		vin3p3-supply = <&vcc_sys_ebc>;
++		wakeup-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
++		ti,up-sequence = <1>, <0>, <2>, <3>;
++		ti,up-delay-ms = <3>, <3>, <3>, <3>;
++		ti,down-sequence = <2>, <3>, <1>, <0>;
++		ti,down-delay-ms = <3>, <6>, <6>, <6>;
++
++		regulators {
++			v3p3: v3p3 {
++				regulator-name = "v3p3";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			vcom: vcom {
++				regulator-name = "vcom";
++				regulator-min-microvolt = <1450000>;
++				regulator-max-microvolt = <1450000>;
++			};
++
++			vdrive: vdrive {
++				regulator-name = "vdrive";
++				regulator-min-microvolt = <15000000>;
++				regulator-max-microvolt = <15000000>;
++			};
++		};
+ 	};
+ };
+ 
+@@ -489,6 +684,10 @@
+  * pin 5 - i2c3_scl_m0, pullup to vcc_3v3
+  */
+ &i2c3 {
++	status = "okay";
++};
++
++&i2s0_8ch {
+ 	status = "okay";
+ };
+ 
+@@ -509,6 +708,14 @@
+ 	};
+ };
+ 
++&pcie2x1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_reset_h>;
++	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
++	status = "okay";
++	vpcie3v3-supply = <&vcc3v3_pcie_p>;
++};
++
+ &pinctrl {
+ 	bt {
+ 		bt_enable_h: bt-enable-h {
+@@ -524,6 +731,27 @@
+ 		};
+ 	};
+ 
++	ebc_pmic {
++		ebc_pmic_pins: ebc-pmic-pins {
++			rockchip,pins = /* wakeup */
++					<4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,
++					/* int */
++					<4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
++					/* pwr_good */
++					<4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
++					/* pwrup */
++					<4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
++					/* vcom_ctrl */
++					<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	fan {
++		fan_en_h: fan-en-h {
++			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	leds {
+ 		work_led_enable_h: work-led-enable-h {
+ 			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+@@ -534,21 +762,49 @@
+ 		};
+ 	};
+ 
++	pcie {
++		pcie_enable_h: pcie-enable-h {
++			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pcie_reset_h: pcie-reset-h {
++			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+ 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+ 
++	usb2 {
++		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
++			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	sdio-pwrseq {
+ 		wifi_enable_h: wifi-enable-h {
+ 			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+ 
++	vcc_lcd_en {
++		vcc_lcd_en_h: vcc-lcd-en-h {
++			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	vcc_sd {
+ 		vcc_sd_h: vcc-sd-h {
+ 			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	vcc_sys_ebc {
++		vcc_sys_ebc_h: vcc-sys-ebc-h {
++			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+ };
+@@ -566,10 +822,23 @@
+ 	status = "okay";
+ };
+ 
++/* sata1 is muxed with the usb3 port */
++&sata1 {
++	status = "disabled";
++};
++
++/* sata2 is muxed with the pcie2 slot*/
++&sata2 {
++	target-supply = <&vcc3v3_pcie_p>;
++	status = "disabled";
++};
++
+ &sdhci {
+ 	bus-width = <8>;
+ 	mmc-hs200-1_8v;
+ 	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ 	vmmc-supply = <&vcc_3v3>;
+ 	vqmmc-supply = <&vcc_1v8>;
+ 	status = "okay";
+@@ -582,6 +851,7 @@
+ 	disable-wp;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	sd-uhs-sdr104;
+ 	vmmc-supply = <&vcc3v3_sd>;
+ 	vqmmc-supply = <&vccio_sd>;
+ 	status = "okay";
+@@ -591,6 +861,7 @@
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
+ 	cap-sdio-irq;
++	disable-wp;
+ 	keep-power-in-suspend;
+ 	mmc-pwrseq = <&sdio_pwrseq>;
+ 	non-removable;
+@@ -600,6 +871,21 @@
+ 	vmmc-supply = <&vcc_wl>;
+ 	vqmmc-supply = <&vcc_1v8>;
+ 	status = "okay";
++};
++
++&sfc {
++	pinctrl-0 = <&fspi_pins>;
++	pinctrl-names = "default";
++	rockchip,sfc-no-dma;
++	status = "okay";
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <50000000>;
++		spi-rx-bus-width = <1>;
++		spi-tx-bus-width = <1>;
++	};
+ };
+ 
+ /* spdif is exposed on con40 pin 18 */
+@@ -664,6 +950,82 @@
+ 	status = "okay";
+ };
+ 
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	status = "okay";
++};
++
++/* usb3 controller is muxed with sata1 */
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb20_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vcc5v0_usb20_otg>;
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	status = "okay";
++};
++
++/* usb3 controller is muxed with sata1 */
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb20_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vcc5v0_usb20_otg>;
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc5v0_usb20_host>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	phy-supply = <&vcc5v0_usb20_host>;
++	status = "okay";
++};
++
+ &vop {
+ 	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ 	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+@@ -680,3 +1042,65 @@
+ 		remote-endpoint = <&hdmi_in_vp0>;
+ 	};
+ };
++
++
++&dsi0 {
++	status = "disabled";
++	clock-master;
++
++	mipi_panel: panel@0 {
++		compatible = "feiyang,fy07024di26a30d";
++		reg = <0>;
++		backlight = <&backlight>;
++		width-mm = <154>;
++		height-mm = <86>;
++		rotation = <0>;
++		dvdd-supply = <&vcc_lcd_en>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@0 {
++				reg = <0>;
++
++				panel_in_dsi: endpoint {
++					remote-endpoint = <&dsi_out_panel>;
++				};
++			};
++		};
++	};
++
++	ports {
++		port@1 {
++			reg = <1>;
++			dsi_out_panel: endpoint {
++				remote-endpoint = <&panel_in_dsi>;
++			};
++		};
++	};
++};
++
++&dsi0_in {
++	dsi0_in_vp1: endpoint@0 {
++		reg = <0>;
++		remote-endpoint = <&vp1_out_dsi0>;
++	};
++};
++
++&video_phy0 {
++	status = "okay";
++};
++
++&vp1 {
++	vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
++		reg = <ROCKCHIP_VOP2_EP_MIPI0>;
++		remote-endpoint = <&dsi0_in_vp1>;
++	};
++};
++
++&pwm14 {
++	status = "okay";
++	pinctrl-0 = <&pwm14m1_pins>;
++	pinctrl-names = "default";
++};
+

patch/kernel/archive/media-5.17/05-v95-rk3568-firefly-roc-pc.patch

@@ -2,7 +2,7 @@ new file mode 100644
 index 000000000..fac2db500
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts
-@@ -0,0 +1,1003 @@
+@@ -0,0 +1,1000 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
@@ -131,7 +131,7 @@ index 000000000..fac2db500
 +		vin-supply = <&dc_12v>;
 +	};
 +
-+	vcc5v0_sys: vcc5v0-sys {
++	vcc5v0_sys: vcc5v0_sys {
 +		compatible = "regulator-fixed";
 +		regulator-name = "vcc5v0_sys";
 +		regulator-always-on;
@@ -213,7 +213,6 @@ index 000000000..fac2db500
 +	firefly_leds: leds {
 +		status = "okay";
 +		compatible = "gpio-leds";
-+
 +		power_led: power {
 +			label = "firefly:blue:power";
 +			linux,default-trigger = "ir-power-click";
@@ -234,17 +233,12 @@ index 000000000..fac2db500
 +	};
 +
 +	sdio_pwrseq: sdio-pwrseq {
++		status = "okay";
 +		compatible = "mmc-pwrseq-simple";
 +		clocks = <&rk809 1>;
 +		clock-names = "ext_clock";
 +		pinctrl-names = "default";
 +		pinctrl-0 = <&wifi_enable_h>;
-+		/*
-+			* On the module itself this is one of these (depending
-+			* on the actual card populated):
-+			* - SDIO_RESET_L_WL_REG_ON
-+			* - PDN (power down when low)
-+		*/
 +		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
 +	};
 +
@@ -697,6 +691,10 @@ index 000000000..fac2db500
 +				};
 +			};
 +		};
++
++		codec {
++			mic-in-differential;
++		};
 +	};
 +};
 +
@@ -766,6 +764,23 @@ index 000000000..fac2db500
 +		};
 +	};
 +
++	pmic {
++		pmic_int: pmic_int {
++			rockchip,pins =
++				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	usb {
++		vcc5v0_host_en: vcc5v0-host-en {
++			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_otg_en: vcc5v0-otg-en {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
 +	usb {
 +		vcc_hub_power_en: vcc-hub-power-en {
 +			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -788,31 +803,14 @@ index 000000000..fac2db500
 +		};
 +	};
 +
-+	pmic {
-+		pmic_int: pmic_int {
-+			rockchip,pins =
-+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	usb {
-+		vcc5v0_host_en: vcc5v0-host-en {
-+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		vcc5v0_otg_en: vcc5v0-otg-en {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
 +	leds {
-+	    led_power: led-power {
-+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+	    };
++		led_power: led-power {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
 +
-+	    led_user: led-user {
-+			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+	    };
++		led_user: led-user {
++			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
 +	};
 +
 +	headphone {
@@ -916,34 +914,6 @@ index 000000000..fac2db500
 +	status = "okay";
 +};
 +
-+&u2phy0_host {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	vbus-supply = <&vcc5v0_otg>;
-+	status = "okay";
-+};
-+
-+&u2phy1_host {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&u2phy0 {
-+	status = "okay";
-+};
-+
-+&u2phy1 {
-+	status = "okay";
-+};
-+
 +&usb_host0_ehci {
 +	status = "okay";
 +};
@@ -952,6 +922,10 @@ index 000000000..fac2db500
 +	status = "okay";
 +};
 +
++&usb_host0_xhci {
++	status = "okay";
++};
++
 +&usb_host1_ehci {
 +	status = "okay";
 +};
@@ -960,23 +934,46 @@ index 000000000..fac2db500
 +	status = "okay";
 +};
 +
-+//&usbdrd_dwc3 {
-+//	dr_mode = "otg";
-+//	extcon = <&u2phy0>;
-+//	status = "okay";
-+//};
 +
-+&usbdrd30 {
++&usb_host1_xhci {
 +	status = "okay";
 +};
 +
-+//&usbhost_dwc3 {
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	vbus-supply = <&vcc5v0_otg>;
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++//&usbdrd30 {
 +//	status = "okay";
 +//};
 +
-+&usbhost30 {
-+	status = "okay";
-+};
++//&usbhost30 {
++//	status = "okay";
++//};
 +
 +&pwm4 {
 +	status = "okay";

patch/kernel/archive/media-5.17/05-v96-rk3566.patch

@@ -7,20 +7,19 @@
 +};
 +
 +&pipegrf {
-+	compatible = "rockchip,rk3566-pipegrf", "syscon";
++	compatible = "rockchip,rk3566-pipe-grf", "syscon";
  };
  
  &power {
-@@ -19,6 +23,14 @@
+@@ -19,6 +23,13 @@
  	};
  };
  
-+&usbdrd30 {
-+	phys = <&u2phy0_otg>;
++&usb_host0_xhci {
++	phys = <&usb2phy0_otg>;
 +	phy-names = "usb2-phy";
-+	extcon = <&u2phy0>;
++	extcon = <&usb2phy0>;
 +	maximum-speed = "high-speed";
-+	snps,dis_u2_susphy_quirk;
 +};
 +
  &vop {

patch/kernel/archive/media-5.17/05-v96-rk3568.patch

@@ -22,23 +22,23 @@
  
  	pipe_phy_grf0: syscon@fdc70000 {
  		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
-@@ -101,6 +116,10 @@
+@@ -99,6 +114,10 @@
  	};
  };
  
 +&pipegrf {
-+	compatible = "rockchip,rk3568-pipegrf", "syscon";
++	compatible = "rockchip,rk3568-pipe-grf", "syscon";
 +};
 +
  &power {
  	power-domain@RK3568_PD_PIPE {
  		reg = <RK3568_PD_PIPE>;
-@@ -117,6 +136,11 @@
+@@ -115,6 +134,11 @@
  	};
  };
  
-+&usbdrd30 {
-+	phys = <&u2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
++&usb_host0_xhci {
++	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
 +	phy-names = "usb2-phy", "usb3-phy";
 +};
 +

patch/kernel/archive/media-5.17/05-v96-rk356x.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -251,16 +251,141 @@
+@@ -251,16 +251,131 @@
  		};
  	};
  
@@ -34,47 +34,37 @@
 +		status = "disabled";
 +	};
 +
-+	usbdrd30: usbdrd {
-+		compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3", "snps,dwc3";
++	usb_host0_xhci: usb@fcc00000 {
++		compatible = "snps,dwc3";
 +		reg = <0x0 0xfcc00000 0x0 0x400000>;
 +		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 +		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
-+			 <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
++			 <&cru ACLK_USB3OTG0>;
 +		clock-names = "ref_clk", "suspend_clk",
-+			      "bus_clk", "pipe_clk";
++			      "bus_clk";
 +		dr_mode = "host";
 +		phy_type = "utmi_wide";
 +		power-domains = <&power RK3568_PD_PIPE>;
 +		resets = <&cru SRST_USB3OTG0>;
-+		reset-names = "usb3-otg";
-+		snps,dis_enblslpm_quirk;
-+		snps,dis-u2-freeclk-exists-quirk;
-+		snps,dis-del-phy-power-chg-quirk;
-+		snps,dis-tx-ipgap-linecheck-quirk;
-+		snps,xhci-trb-ent-quirk;
++		snps,dis_u2_susphy_quirk;
 +		status = "disabled";
 +	};
 +
-+	usbhost30: usbhost {
-+		compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3", "snps,dwc3";
++	usb_host1_xhci: usb@fd000000 {
++		compatible = "snps,dwc3";
 +		reg = <0x0 0xfd000000 0x0 0x400000>;
 +		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 +		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
-+			 <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
++			 <&cru ACLK_USB3OTG1>;
 +		clock-names = "ref_clk", "suspend_clk",
-+			      "bus_clk", "pipe_clk";
++			      "bus_clk";
 +		dr_mode = "host";
-+		phys = <&u2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
++		phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
 +		phy-names = "usb2-phy", "usb3-phy";
 +		phy_type = "utmi_wide";
 +		power-domains = <&power RK3568_PD_PIPE>;
 +		resets = <&cru SRST_USB3OTG1>;
-+		reset-names = "usb3-host";
-+		snps,dis_enblslpm_quirk;
-+		snps,dis-u2-freeclk-exists-quirk;
 +		snps,dis_u2_susphy_quirk;
-+		snps,dis-del-phy-power-chg-quirk;
-+		snps,dis-tx-ipgap-linecheck-quirk;
 +		status = "disabled";
 +	};
 +
@@ -106,7 +96,7 @@
 +		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 +		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 +			 <&cru PCLK_USB>;
-+		phys = <&u2phy1_otg>;
++		phys = <&usb2phy1_otg>;
 +		phy-names = "usb";
 +		status = "disabled";
 +	};
@@ -117,7 +107,7 @@
 +		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 +		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 +			 <&cru PCLK_USB>;
-+		phys = <&u2phy1_otg>;
++		phys = <&usb2phy1_otg>;
 +		phy-names = "usb";
 +		status = "disabled";
 +	};
@@ -128,7 +118,7 @@
 +		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 +		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 +			 <&cru PCLK_USB>;
-+		phys = <&u2phy1_host>;
++		phys = <&usb2phy1_host>;
 +		phy-names = "usb";
 +		status = "disabled";
 +	};
@@ -139,13 +129,21 @@
 +		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 +		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 +			 <&cru PCLK_USB>;
-+		phys = <&u2phy1_host>;
++		phys = <&usb2phy1_host>;
 +		phy-names = "usb";
 +		status = "disabled";
  	};
  
  	pmugrf: syscon@fdc20000 {
-@@ -291,6 +416,16 @@
+@@ -274,7 +389,6 @@
+ 	};
+ 
+ 	pipegrf: syscon@fdc50000 {
+-		compatible = "rockchip,rk3568-pipe-grf", "syscon";
+ 		reg = <0x0 0xfdc50000 0x0 0x1000>;
+ 	};
+ 
+@@ -291,6 +405,16 @@
  	pipe_phy_grf2: syscon@fdc90000 {
  		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
  		reg = <0x0 0xfdc90000 0x0 0x1000>;
@@ -162,7 +160,7 @@
  	};
  
  	pmucru: clock-controller@fdd00000 {
-@@ -330,6 +465,7 @@
+@@ -330,6 +454,7 @@
  		clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 0>, <&dmac0 1>;
@@ -170,11 +168,10 @@
  		pinctrl-0 = <&uart0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -472,6 +608,28 @@
- 		#cooling-cells = <2>;
- 		operating-points-v2 = <&gpu_opp_table>;
- 		power-domains = <&power RK3568_PD_GPU>;
-+		status = "disabled";
+@@ -495,6 +620,28 @@
+ 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ 		power-domains = <&power RK3568_PD_VPU>;
+ 		#iommu-cells = <0>;
 +	};
 +
 +	ebc: ebc@fdec0000 {
@@ -196,13 +193,94 @@
 +		clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
 +		clock-names = "pclk", "hclk";
 +		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++		status = "disabled";
+ 	};
+ 
+ 	sdmmc2: mmc@fe000000 {
+@@ -604,6 +751,62 @@
  		status = "disabled";
  	};
  
-@@ -737,6 +895,61 @@
- 		reg = <0x0 0xfe1a8100 0x0 0x20>;
- 	};
++	dsi0: dsi@fe060000 {
++		compatible = "rockchip,rk3568-mipi-dsi";
++		reg = <0x0 0xfe060000 0x0 0x10000>;
++		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>;
++		clock-names = "pclk", "hclk", "hs_clk";
++		phys = <&video_phy0>;
++		phy-names = "dphy";
++		power-domains = <&power RK3568_PD_VO>;
++		resets = <&cru SRST_P_DSITX_0>;
++		reset-names = "apb";
++		rockchip,grf = <&grf>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			dsi0_in: port@0 {
++				reg = <0>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++	};
++
++	dsi1: dsi@fe070000 {
++		compatible = "rockchip,rk3568-mipi-dsi";
++		reg = <0x0 0xfe070000 0x0 0x10000>;
++		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>;
++		clock-names = "pclk", "hclk", "hs_clk";
++		phys = <&video_phy1>;
++		phy-names = "dphy";
++		power-domains = <&power RK3568_PD_VO>;
++		resets = <&cru SRST_P_DSITX_1>;
++		reset-names = "apb";
++		rockchip,grf = <&grf>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			dsi1_in: port@0 {
++				reg = <0>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++	};
++
+ 	hdmi: hdmi@fe0a0000 {
+ 		compatible = "rockchip,rk3568-dw-hdmi";
+ 		reg = <0x0 0xfe0a0000 0x0 0x20000>;
+@@ -628,10 +831,14 @@
  
+ 			hdmi_in: port@0 {
+ 				reg = <0>;
++				#address-cells = <1>;
++				#size-cells = <0>;
+ 			};
+ 
+ 			hdmi_out: port@1 {
+ 				reg = <1>;
++				#address-cells = <1>;
++				#size-cells = <0>;
+ 			};
+ 		};
+ 	};
+@@ -754,6 +961,61 @@
+ 	qos_vop_m1: qos@fe1a8100 {
+ 		compatible = "rockchip,rk3568-qos", "syscon";
+ 		reg = <0x0 0xfe1a8100 0x0 0x20>;
++	};
++
 +	pcie2x1: pcie@fe260000 {
 +		compatible = "rockchip,rk3568-pcie";
 +		#address-cells = <3>;
@@ -256,12 +334,10 @@
 +			interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
 +		};
 +
-+	};
-+
+ 	};
+ 
  	sdmmc0: mmc@fe2b0000 {
- 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
- 		reg = <0x0 0xfe2b0000 0x0 0x4000>;
-@@ -762,6 +975,17 @@
+@@ -781,6 +1043,19 @@
  		max-frequency = <150000000>;
  		resets = <&cru SRST_SDMMC1>;
  		reset-names = "reset";
@@ -274,12 +350,14 @@
 +		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 +		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 +		clock-names = "clk_sfc", "hclk_sfc";
-+		pinctrl-0 = <&fspi_pins>;
-+		pinctrl-names = "default";
++		assigned-clocks = <&cru SCLK_SFC>;
++		assigned-clock-rates = <100000000>;
++		#address-cells = <1>;
++		#size-cells = <0>;
  		status = "disabled";
  	};
  
-@@ -834,6 +1058,43 @@
+@@ -853,6 +1128,43 @@
  		status = "disabled";
  	};
  
@@ -323,7 +401,7 @@
  	dmac0: dma-controller@fe530000 {
  		compatible = "arm,pl330", "arm,primecell";
  		reg = <0x0 0xfe530000 0x0 0x4000>;
-@@ -996,6 +1257,7 @@
+@@ -1015,6 +1327,7 @@
  		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 2>, <&dmac0 3>;
@@ -331,7 +409,7 @@
  		pinctrl-0 = <&uart1m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1010,6 +1272,7 @@
+@@ -1029,6 +1342,7 @@
  		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 4>, <&dmac0 5>;
@@ -339,7 +417,7 @@
  		pinctrl-0 = <&uart2m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1024,6 +1287,7 @@
+@@ -1043,6 +1357,7 @@
  		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 6>, <&dmac0 7>;
@@ -347,7 +425,7 @@
  		pinctrl-0 = <&uart3m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1038,6 +1302,7 @@
+@@ -1057,6 +1372,7 @@
  		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 8>, <&dmac0 9>;
@@ -355,7 +433,7 @@
  		pinctrl-0 = <&uart4m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1052,6 +1317,7 @@
+@@ -1071,6 +1387,7 @@
  		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 10>, <&dmac0 11>;
@@ -363,7 +441,7 @@
  		pinctrl-0 = <&uart5m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1066,6 +1332,7 @@
+@@ -1085,6 +1402,7 @@
  		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 12>, <&dmac0 13>;
@@ -371,7 +449,7 @@
  		pinctrl-0 = <&uart6m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1080,6 +1347,7 @@
+@@ -1099,6 +1417,7 @@
  		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 14>, <&dmac0 15>;
@@ -379,7 +457,7 @@
  		pinctrl-0 = <&uart7m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1094,6 +1362,7 @@
+@@ -1113,6 +1432,7 @@
  		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 16>, <&dmac0 17>;
@@ -387,7 +465,7 @@
  		pinctrl-0 = <&uart8m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1108,6 +1377,7 @@
+@@ -1127,10 +1447,41 @@
  		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
  		clock-names = "baudclk", "apb_pclk";
  		dmas = <&dmac0 18>, <&dmac0 19>;
@@ -395,11 +473,77 @@
  		pinctrl-0 = <&uart9m0_xfer>;
  		pinctrl-names = "default";
  		reg-io-width = <4>;
-@@ -1383,6 +1653,50 @@
+ 		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	video_phy0: video-phy@fe850000 {
++		compatible = "rockchip,rk3568-video-phy";
++		reg = <0x0 0xfe850000  0x0 0x10000>,
++		      <0x0 0xfe060000 0x0 0x10000>;
++		clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
++			 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
++		clock-names = "ref", "pclk_phy", "pclk_host";
++		#clock-cells = <0>;
++		resets = <&cru SRST_P_MIPIDSIPHY0>;
++		reset-names = "rst";
++		power-domains = <&power RK3568_PD_VO>;
++		#phy-cells = <0>;
++		status = "disabled";
++	};
++
++	video_phy1: video-phy@fe860000 {
++		compatible = "rockchip,rk3568-video-phy";
++		reg = <0x0 0xfe860000  0x0 0x10000>,
++		      <0x0 0xfe070000 0x0 0x10000>;
++		clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
++			 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
++		clock-names = "ref", "pclk_phy", "pclk_host";
++		#clock-cells = <0>;
++		resets = <&cru SRST_P_MIPIDSIPHY1>;
++		reset-names = "rst";
++		power-domains = <&power RK3568_PD_VO>;
++		#phy-cells = <0>;
  		status = "disabled";
  	};
  
-+	u2phy0: usb2phy@fe8a0000 {
+@@ -1370,6 +1721,82 @@
+ 		status = "disabled";
+ 	};
+ 
++//	combphy1: phy@fe830000 {
++//		compatible = "rockchip,rk3568-naneng-combphy";
++//		reg = <0x0 0xfe830000 0x0 0x100>;
++//		clocks = <&pmucru CLK_PCIEPHY1_REF>,
++//			 <&cru PCLK_PIPEPHY1>,
++//			 <&cru PCLK_PIPE>;
++//		clock-names = "ref", "apb", "pipe";
++//		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
++//		assigned-clock-rates = <100000000>;
++//		resets = <&cru SRST_PIPEPHY1>;
++//		rockchip,pipe-grf = <&pipegrf>;
++//		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
++//		#phy-cells = <1>;
++//		status = "disabled";
++//	};
++
++//	combphy2: phy@fe840000 {
++//		compatible = "rockchip,rk3568-naneng-combphy";
++//		reg = <0x0 0xfe840000 0x0 0x100>;
++//		clocks = <&pmucru CLK_PCIEPHY2_REF>,
++//			 <&cru PCLK_PIPEPHY2>,
++//			 <&cru PCLK_PIPE>;
++//		clock-names = "ref", "apb", "pipe";
++//		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
++//		assigned-clock-rates = <100000000>;
++//		resets = <&cru SRST_PIPEPHY2>;
++//		rockchip,pipe-grf = <&pipegrf>;
++//		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
++//		#phy-cells = <1>;
++//		status = "disabled";
++//	};
++
++	usb2phy0: usb2phy@fe8a0000 {
 +		compatible = "rockchip,rk3568-usb2phy";
 +		reg = <0x0 0xfe8a0000 0x0 0x10000>;
 +		clocks = <&pmucru CLK_USBPHY0_REF>;
@@ -410,18 +554,18 @@
 +		#clock-cells = <0>;
 +		status = "disabled";
 +
-+		u2phy0_host: host-port {
++		usb2phy0_host: host-port {
 +			#phy-cells = <0>;
 +			status = "disabled";
 +		};
 +
-+		u2phy0_otg: otg-port {
++		usb2phy0_otg: otg-port {
 +			#phy-cells = <0>;
 +			status = "disabled";
 +		};
 +	};
 +
-+	u2phy1: usb2phy@fe8b0000 {
++	usb2phy1: usb2phy@fe8b0000 {
 +		compatible = "rockchip,rk3568-usb2phy";
 +		reg = <0x0 0xfe8b0000 0x0 0x10000>;
 +		clocks = <&pmucru CLK_USBPHY1_REF>;
@@ -432,12 +576,12 @@
 +		#clock-cells = <0>;
 +		status = "disabled";
 +
-+		u2phy1_host: host-port {
++		usb2phy1_host: host-port {
 +			#phy-cells = <0>;
 +			status = "disabled";
 +		};
 +
-+		u2phy1_otg: otg-port {
++		usb2phy1_otg: otg-port {
 +			#phy-cells = <0>;
 +			status = "disabled";
 +		};

patch/kernel/archive/media-5.17/09-linux-0011-v4l2-from-list.patch

@@ -1,734 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:33 +0000
-Subject: [PATCH] media: rkvdec: h264: Fix reference frame_num wrap for second
- field
-
-When decoding the second field in a complementary field pair the second
-field is sharing the same frame_num with the first field.
-
-Currently the frame_num for the first field is wrapped when it matches the
-field being decoded, this cause issues to decode the second field in a
-complementary field pair.
-
-Fix this by using inclusive comparison, less than or equal.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
----
- drivers/staging/media/rkvdec/rkvdec-h264.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
-index 951e19231da2..3becb0186062 100644
---- a/drivers/staging/media/rkvdec/rkvdec-h264.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
-@@ -752,7 +752,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- 			continue;
- 
- 		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM ||
--		    dpb[i].frame_num < dec_params->frame_num) {
-+		    dpb[i].frame_num <= dec_params->frame_num) {
- 			p[i] = dpb[i].frame_num;
- 			continue;
- 		}
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:34 +0000
-Subject: [PATCH] media: rkvdec: Ensure decoded resolution fit coded resolution
-
-Ensure decoded CAPTURE buffer resolution is larger or equal to the coded
-OPTUPT buffer resolution.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/staging/media/rkvdec/rkvdec.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index ad2624c30843..efd316550807 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -268,6 +268,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
- 		pix_mp->pixelformat = coded_desc->decoded_fmts[0];
- 
- 	/* Always apply the frmsize constraint of the coded end. */
-+	pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
-+	pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height);
- 	v4l2_apply_frmsize_constraints(&pix_mp->width,
- 				       &pix_mp->height,
- 				       &coded_desc->frmsize);
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:34 +0000
-Subject: [PATCH] media: rkvdec: h264: Validate and use pic width and height in
- mbs
-
-The width and height in mbs is currently configured based on OUTPUT buffer
-resolution, this works for frame pictures but can cause issues for field
-pictures.
-
-When frame_mbs_only_flag is 0 the height in mbs should be height of
-the field instead of height of frame.
-
-Validate pic_width_in_mbs_minus1 and pic_height_in_map_units_minus1
-against OUTPUT buffer resolution and use these values to configure HW.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/staging/media/rkvdec/rkvdec-h264.c |  4 ++--
- drivers/staging/media/rkvdec/rkvdec.c      | 10 ++++++++++
- 2 files changed, 12 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
-index 3becb0186062..a379e43147fb 100644
---- a/drivers/staging/media/rkvdec/rkvdec-h264.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
-@@ -671,8 +671,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
- 		  LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4);
- 	WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO),
- 		  DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG);
--	WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.width, 16), PIC_WIDTH_IN_MBS);
--	WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.height, 16), PIC_HEIGHT_IN_MBS);
-+	WRITE_PPS(sps->pic_width_in_mbs_minus1 + 1, PIC_WIDTH_IN_MBS);
-+	WRITE_PPS(sps->pic_height_in_map_units_minus1 + 1, PIC_HEIGHT_IN_MBS);
- 	WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY),
- 		  FRAME_MBS_ONLY_FLAG);
- 	WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD),
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index efd316550807..c88e817cac0a 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -29,8 +29,11 @@
- 
- static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
- {
-+	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
-+
- 	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
- 		const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
-+		unsigned int width, height;
- 		/*
- 		 * TODO: The hardware supports 10-bit and 4:2:2 profiles,
- 		 * but it's currently broken in the driver.
-@@ -45,6 +48,13 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
- 		if (sps->bit_depth_luma_minus8 != 0)
- 			/* Only 8-bit is supported */
- 			return -EINVAL;
-+
-+		width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
-+		height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
-+
-+		if (width > ctx->coded_fmt.fmt.pix_mp.width ||
-+		    height > ctx->coded_fmt.fmt.pix_mp.height)
-+			return -EINVAL;
- 	}
- 	return 0;
- }
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:35 +0000
-Subject: [PATCH] media: rkvdec: h264: Fix bit depth wrap in pps packet
-
-The luma and chroma bit depth fields in the pps packet is 3 bits wide.
-8 is wrongly added to the bit depth value written to these 3-bit fields.
-Because only the 3 LSB is written the hardware is configured correctly.
-
-Correct this by not adding 8 to the luma and chroma bit depth value.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
----
- drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
-index a379e43147fb..503ae683d0fd 100644
---- a/drivers/staging/media/rkvdec/rkvdec-h264.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
-@@ -661,8 +661,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
- 	WRITE_PPS(0xff, PROFILE_IDC);
- 	WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
- 	WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
--	WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
--	WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
-+	WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
-+	WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
- 	WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
- 	WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
- 	WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:35 +0000
-Subject: [PATCH] media: v4l2-common: Add helpers to calculate bytesperline and
- sizeimage
-
-Add helper functions to calculate plane bytesperline and sizeimage, these
-new helpers consider block width and height when calculating plane
-bytesperline and sizeimage.
-
-This prepare support for new pixel formats added in next patch that make
-use of block width and height.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++--------------
- 1 file changed, 38 insertions(+), 39 deletions(-)
-
-diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
-index df34b2a283bc..287488016ff2 100644
---- a/drivers/media/v4l2-core/v4l2-common.c
-+++ b/drivers/media/v4l2-core/v4l2-common.c
-@@ -336,6 +336,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
- 	return info->block_h[plane];
- }
- 
-+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane,
-+						   unsigned int width)
-+{
-+	unsigned int hdiv = plane ? info->hdiv : 1;
-+	unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane],
-+				v4l2_format_block_width(info, plane) *
-+				v4l2_format_block_height(info, plane));
-+
-+	return DIV_ROUND_UP(bytes, hdiv);
-+}
-+
-+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane,
-+						    unsigned int height)
-+{
-+	unsigned int vdiv = plane ? info->vdiv : 1;
-+	unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane));
-+
-+	return DIV_ROUND_UP(lines, vdiv);
-+}
-+
-+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane,
-+						  unsigned int width, unsigned int height)
-+{
-+	return v4l2_format_plane_width(info, plane, width) *
-+	       v4l2_format_plane_height(info, plane, height);
-+}
-+
- void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
- 				    const struct v4l2_frmsize_stepwise *frmsize)
- {
-@@ -371,37 +398,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
- 
- 	if (info->mem_planes == 1) {
- 		plane = &pixfmt->plane_fmt[0];
--		plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0];
-+		plane->bytesperline = v4l2_format_plane_width(info, 0, width);
- 		plane->sizeimage = 0;
- 
--		for (i = 0; i < info->comp_planes; i++) {
--			unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
--			unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
--			unsigned int aligned_width;
--			unsigned int aligned_height;
--
--			aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
--			aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
--
--			plane->sizeimage += info->bpp[i] *
--				DIV_ROUND_UP(aligned_width, hdiv) *
--				DIV_ROUND_UP(aligned_height, vdiv);
--		}
-+		for (i = 0; i < info->comp_planes; i++)
-+			plane->sizeimage +=
-+				v4l2_format_plane_size(info, i, width, height);
- 	} else {
- 		for (i = 0; i < info->comp_planes; i++) {
--			unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
--			unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
--			unsigned int aligned_width;
--			unsigned int aligned_height;
--
--			aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
--			aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
--
- 			plane = &pixfmt->plane_fmt[i];
- 			plane->bytesperline =
--				info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv);
--			plane->sizeimage =
--				plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv);
-+				v4l2_format_plane_width(info, i, width);
-+			plane->sizeimage = plane->bytesperline *
-+				v4l2_format_plane_height(info, i, height);
- 		}
- 	}
- 	return 0;
-@@ -425,22 +434,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
- 	pixfmt->width = width;
- 	pixfmt->height = height;
- 	pixfmt->pixelformat = pixelformat;
--	pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0];
-+	pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width);
- 	pixfmt->sizeimage = 0;
- 
--	for (i = 0; i < info->comp_planes; i++) {
--		unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
--		unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
--		unsigned int aligned_width;
--		unsigned int aligned_height;
--
--		aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
--		aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
--
--		pixfmt->sizeimage += info->bpp[i] *
--			DIV_ROUND_UP(aligned_width, hdiv) *
--			DIV_ROUND_UP(aligned_height, vdiv);
--	}
-+	for (i = 0; i < info->comp_planes; i++)
-+		pixfmt->sizeimage +=
-+			v4l2_format_plane_size(info, i, width, height);
- 	return 0;
- }
- EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:36 +0000
-Subject: [PATCH] media: v4l2: Add NV15 and NV20 pixel formats
-
-Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for
-10-bit buffers.
-
-NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/CbCr format
-similar to P010 and P210 but has no padding between components. Instead,
-luminance and chrominance samples are grouped into 4s so that each group is
-packed into an integer number of bytes:
-
-YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
-
-The '15' and '20' suffix refers to the optimum effective bits per pixel
-which is achieved when the total number of luminance samples is a multiple
-of 8 for NV15 and 4 for NV20.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/media/v4l2-core/v4l2-common.c | 3 +++
- drivers/media/v4l2-core/v4l2-ioctl.c  | 2 ++
- include/uapi/linux/videodev2.h        | 3 +++
- 3 files changed, 8 insertions(+)
-
-diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
-index 287488016ff2..01f8a50586eb 100644
---- a/drivers/media/v4l2-core/v4l2-common.c
-+++ b/drivers/media/v4l2-core/v4l2-common.c
-@@ -267,6 +267,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
- 		{ .format = V4L2_PIX_FMT_NV24,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
- 		{ .format = V4L2_PIX_FMT_NV42,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
- 
-+		{ .format = V4L2_PIX_FMT_NV15,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
-+		{ .format = V4L2_PIX_FMT_NV20,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
-+
- 		{ .format = V4L2_PIX_FMT_YUV410,  .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
- 		{ .format = V4L2_PIX_FMT_YVU410,  .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
- 		{ .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 },
-diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
-index 51289d4741dc..e6f2c65e24ca 100644
---- a/drivers/media/v4l2-core/v4l2-ioctl.c
-+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
-@@ -1299,6 +1299,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
- 	case V4L2_PIX_FMT_NV61:		descr = "Y/CrCb 4:2:2"; break;
- 	case V4L2_PIX_FMT_NV24:		descr = "Y/CbCr 4:4:4"; break;
- 	case V4L2_PIX_FMT_NV42:		descr = "Y/CrCb 4:4:4"; break;
-+	case V4L2_PIX_FMT_NV15:		descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break;
-+	case V4L2_PIX_FMT_NV20:		descr = "10-bit Y/CbCr 4:2:2 (Packed)"; break;
- 	case V4L2_PIX_FMT_NV12_4L4:	descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break;
- 	case V4L2_PIX_FMT_NV12_16L16:	descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break;
- 	case V4L2_PIX_FMT_NV12_32L32:   descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break;
-diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
-index df8b9c486ba1..9845ce720b4e 100644
---- a/include/uapi/linux/videodev2.h
-+++ b/include/uapi/linux/videodev2.h
-@@ -602,6 +602,9 @@ struct v4l2_pix_format {
- #define V4L2_PIX_FMT_NV24    v4l2_fourcc('N', 'V', '2', '4') /* 24  Y/CbCr 4:4:4  */
- #define V4L2_PIX_FMT_NV42    v4l2_fourcc('N', 'V', '4', '2') /* 24  Y/CrCb 4:4:4  */
- 
-+#define V4L2_PIX_FMT_NV15    v4l2_fourcc('N', 'V', '1', '5') /* 15  Y/CbCr 4:2:0 10-bit packed */
-+#define V4L2_PIX_FMT_NV20    v4l2_fourcc('N', 'V', '2', '0') /* 20  Y/CbCr 4:2:2 10-bit packed */
-+
- /* two non contiguous planes - one Y, one Cr + Cb interleaved  */
- #define V4L2_PIX_FMT_NV12M   v4l2_fourcc('N', 'M', '1', '2') /* 12  Y/CbCr 4:2:0  */
- #define V4L2_PIX_FMT_NV21M   v4l2_fourcc('N', 'M', '2', '1') /* 21  Y/CrCb 4:2:0  */
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:36 +0000
-Subject: [PATCH] media: rkvdec: h264: Use bytesperline and buffer height to
- calculate stride
-
-Use bytesperline and buffer height to calculate the strides configured.
-
-This does not really change anything other than ensuring the bytesperline
-that is signaled to userspace matches what is configured in HW.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/staging/media/rkvdec/rkvdec-h264.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
-index 503ae683d0fd..88f5f4bb320b 100644
---- a/drivers/staging/media/rkvdec/rkvdec-h264.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
-@@ -893,9 +893,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
- 	dma_addr_t rlc_addr;
- 	dma_addr_t refer_addr;
- 	u32 rlc_len;
--	u32 hor_virstride = 0;
--	u32 ver_virstride = 0;
--	u32 y_virstride = 0;
-+	u32 hor_virstride;
-+	u32 ver_virstride;
-+	u32 y_virstride;
- 	u32 yuv_virstride = 0;
- 	u32 offset;
- 	dma_addr_t dst_addr;
-@@ -906,8 +906,8 @@ static void config_registers(struct rkvdec_ctx *ctx,
- 
- 	f = &ctx->decoded_fmt;
- 	dst_fmt = &f->fmt.pix_mp;
--	hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8;
--	ver_virstride = round_up(dst_fmt->height, 16);
-+	hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
-+	ver_virstride = dst_fmt->height;
- 	y_virstride = hor_virstride * ver_virstride;
- 
- 	if (sps->chroma_format_idc == 0)
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:37 +0000
-Subject: [PATCH] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt helper
- method
-
-This extract setting decoded pixfmt into a helper method, current code is
-replaced with a call to the new helper method.
-
-The helper method is also called from a new function in next patch.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/staging/media/rkvdec/rkvdec.c | 29 ++++++++++++++-------------
- 1 file changed, 15 insertions(+), 14 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index c88e817cac0a..d4ae792874bb 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -27,6 +27,17 @@
- #include "rkvdec.h"
- #include "rkvdec-regs.h"
- 
-+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
-+				       struct v4l2_pix_format_mplane *pix_mp)
-+{
-+	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
-+			    pix_mp->width, pix_mp->height);
-+	pix_mp->plane_fmt[0].sizeimage += 128 *
-+		DIV_ROUND_UP(pix_mp->width, 16) *
-+		DIV_ROUND_UP(pix_mp->height, 16);
-+	pix_mp->field = V4L2_FIELD_NONE;
-+}
-+
- static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
- {
- 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
-@@ -212,13 +223,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
- 
- 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
- 	f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
--	v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
--			    ctx->coded_fmt_desc->decoded_fmts[0],
--			    ctx->coded_fmt.fmt.pix_mp.width,
--			    ctx->coded_fmt.fmt.pix_mp.height);
--	f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 *
--		DIV_ROUND_UP(f->fmt.pix_mp.width, 16) *
--		DIV_ROUND_UP(f->fmt.pix_mp.height, 16);
-+	f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
-+	f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
-+	rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
- }
- 
- static int rkvdec_enum_framesizes(struct file *file, void *priv,
-@@ -284,13 +291,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
- 				       &pix_mp->height,
- 				       &coded_desc->frmsize);
- 
--	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
--			    pix_mp->width, pix_mp->height);
--	pix_mp->plane_fmt[0].sizeimage +=
--		128 *
--		DIV_ROUND_UP(pix_mp->width, 16) *
--		DIV_ROUND_UP(pix_mp->height, 16);
--	pix_mp->field = V4L2_FIELD_NONE;
-+	rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
- 
- 	return 0;
- }
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:37 +0000
-Subject: [PATCH] media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt
-
-Add an optional valid_fmt operation that should return the valid
-pixelformat of CAPTURE buffers.
-
-This is used in next patch to ensure correct pixelformat is used for 10-bit
-and 4:2:2 content.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/staging/media/rkvdec/rkvdec.c | 59 ++++++++++++++++++++++++---
- drivers/staging/media/rkvdec/rkvdec.h |  2 +
- 2 files changed, 55 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index d4ae792874bb..3cbb1d26b972 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -38,6 +38,16 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
- 	pix_mp->field = V4L2_FIELD_NONE;
- }
- 
-+static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
-+{
-+	const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc;
-+
-+	if (coded_desc->ops->valid_fmt)
-+		return coded_desc->ops->valid_fmt(ctx, ctrl);
-+
-+	return ctx->valid_fmt;
-+}
-+
- static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
- {
- 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
-@@ -60,6 +70,10 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
- 			/* Only 8-bit is supported */
- 			return -EINVAL;
- 
-+		if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
-+			/* Only current valid format */
-+			return -EINVAL;
-+
- 		width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
- 		height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
- 
-@@ -70,8 +84,27 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
- 	return 0;
- }
- 
-+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
-+{
-+	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
-+
-+	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) {
-+		ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
-+		if (ctx->valid_fmt) {
-+			struct v4l2_pix_format_mplane *pix_mp;
-+
-+			pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
-+			pix_mp->pixelformat = ctx->valid_fmt;
-+			rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
- static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
- 	.try_ctrl = rkvdec_try_ctrl,
-+	.s_ctrl = rkvdec_s_ctrl,
- };
- 
- static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
-@@ -221,6 +254,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
- {
- 	struct v4l2_format *f = &ctx->decoded_fmt;
- 
-+	ctx->valid_fmt = 0;
- 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
- 	f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
- 	f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
-@@ -276,13 +310,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
- 	if (WARN_ON(!coded_desc))
- 		return -EINVAL;
- 
--	for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
--		if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
--			break;
--	}
-+	if (ctx->valid_fmt) {
-+		pix_mp->pixelformat = ctx->valid_fmt;
-+	} else {
-+		for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
-+			if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
-+				break;
-+		}
- 
--	if (i == coded_desc->num_decoded_fmts)
--		pix_mp->pixelformat = coded_desc->decoded_fmts[0];
-+		if (i == coded_desc->num_decoded_fmts)
-+			pix_mp->pixelformat = coded_desc->decoded_fmts[0];
-+	}
- 
- 	/* Always apply the frmsize constraint of the coded end. */
- 	pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
-@@ -346,6 +384,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv,
- 		return ret;
- 
- 	ctx->decoded_fmt = *f;
-+	ctx->valid_fmt = f->fmt.pix_mp.pixelformat;
- 	return 0;
- }
- 
-@@ -446,6 +485,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
- 	if (WARN_ON(!ctx->coded_fmt_desc))
- 		return -EINVAL;
- 
-+	if (ctx->valid_fmt) {
-+		if (f->index)
-+			return -EINVAL;
-+
-+		f->pixelformat = ctx->valid_fmt;
-+		return 0;
-+	}
-+
- 	if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
- 		return -EINVAL;
- 
-diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
-index 2f4ea1786b93..c26c472baa6f 100644
---- a/drivers/staging/media/rkvdec/rkvdec.h
-+++ b/drivers/staging/media/rkvdec/rkvdec.h
-@@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
- struct rkvdec_coded_fmt_ops {
- 	int (*adjust_fmt)(struct rkvdec_ctx *ctx,
- 			  struct v4l2_format *f);
-+	u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl);
- 	int (*start)(struct rkvdec_ctx *ctx);
- 	void (*stop)(struct rkvdec_ctx *ctx);
- 	int (*run)(struct rkvdec_ctx *ctx);
-@@ -99,6 +100,7 @@ struct rkvdec_ctx {
- 	struct v4l2_fh fh;
- 	struct v4l2_format coded_fmt;
- 	struct v4l2_format decoded_fmt;
-+	u32 valid_fmt;
- 	const struct rkvdec_coded_fmt_desc *coded_fmt_desc;
- 	struct v4l2_ctrl_handler ctrl_hdl;
- 	struct rkvdec_dev *dev;
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 21:54:37 +0000
-Subject: [PATCH] media: rkvdec: h264: Support High 10 and 4:2:2 profiles
-
-Add support and enable decoding of H264 High 10 and 4:2:2 profiles.
-
-Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW
-requirement on 10-bit format buffers.
-
-The new valid_fmt operation is implemented and return a valid pixelformat
-for the provided SPS control.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/staging/media/rkvdec/rkvdec-h264.c | 20 ++++++++++++++++++++
- drivers/staging/media/rkvdec/rkvdec.c      | 19 +++++++++----------
- 2 files changed, 29 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
-index 88f5f4bb320b..c9a551dbd9bc 100644
---- a/drivers/staging/media/rkvdec/rkvdec-h264.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
-@@ -1021,6 +1021,25 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx,
- 	return 0;
- }
- 
-+static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
-+{
-+	const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
-+
-+	if (sps->bit_depth_luma_minus8 == 0) {
-+		if (sps->chroma_format_idc == 2)
-+			return V4L2_PIX_FMT_NV16;
-+		else
-+			return V4L2_PIX_FMT_NV12;
-+	} else if (sps->bit_depth_luma_minus8 == 2) {
-+		if (sps->chroma_format_idc == 2)
-+			return V4L2_PIX_FMT_NV20;
-+		else
-+			return V4L2_PIX_FMT_NV15;
-+	}
-+
-+	return 0;
-+}
-+
- static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
- {
- 	struct rkvdec_dev *rkvdec = ctx->dev;
-@@ -1124,6 +1143,7 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx)
- 
- const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
- 	.adjust_fmt = rkvdec_h264_adjust_fmt,
-+	.valid_fmt = rkvdec_h264_valid_fmt,
- 	.start = rkvdec_h264_start,
- 	.stop = rkvdec_h264_stop,
- 	.run = rkvdec_h264_run,
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index 3cbb1d26b972..bd106b23f4a0 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
- 				       struct v4l2_pix_format_mplane *pix_mp)
- {
- 	v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
--			    pix_mp->width, pix_mp->height);
-+			    ALIGN(pix_mp->width, 64), pix_mp->height);
- 	pix_mp->plane_fmt[0].sizeimage += 128 *
- 		DIV_ROUND_UP(pix_mp->width, 16) *
- 		DIV_ROUND_UP(pix_mp->height, 16);
-@@ -55,19 +55,15 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
- 	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
- 		const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
- 		unsigned int width, height;
--		/*
--		 * TODO: The hardware supports 10-bit and 4:2:2 profiles,
--		 * but it's currently broken in the driver.
--		 * Reject them for now, until it's fixed.
--		 */
--		if (sps->chroma_format_idc > 1)
--			/* Only 4:0:0 and 4:2:0 are supported */
-+
-+		if (sps->chroma_format_idc > 2)
-+			/* Only 4:0:0, 4:2:0 and 4:2:2 are supported */
- 			return -EINVAL;
- 		if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
- 			/* Luma and chroma bit depth mismatch */
- 			return -EINVAL;
--		if (sps->bit_depth_luma_minus8 != 0)
--			/* Only 8-bit is supported */
-+		if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
-+			/* Only 8-bit and 10-bit is supported */
- 			return -EINVAL;
- 
- 		if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
-@@ -155,6 +151,9 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
- 
- static const u32 rkvdec_h264_vp9_decoded_fmts[] = {
- 	V4L2_PIX_FMT_NV12,
-+	V4L2_PIX_FMT_NV15,
-+	V4L2_PIX_FMT_NV16,
-+	V4L2_PIX_FMT_NV20,
- };
- 
- static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = {

patch/kernel/archive/media-5.17/09-linux-0020-drm-from-list.patch

@@ -1,364 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 22:30:13 +0000
-Subject: [PATCH] drm: drm_fourcc: add NV20 and NV30 YUV formats
-
-DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
-variant of NV15, a 10-bit 2-plane YUV format that has no padding between
-components. Instead, luminance and chrominance samples are grouped into 4s
-so that each group is packed into an integer number of bytes:
-
-YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
-
-The '20' and '30' suffix refers to the optimum effective bits per pixel
-which is achieved when the total number of luminance samples is a multiple
-of 4.
-
-V2: Added NV30 format
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Sandy Huang <hjc@rock-chips.com>
----
- drivers/gpu/drm/drm_fourcc.c  | 8 ++++++++
- include/uapi/drm/drm_fourcc.h | 2 ++
- 2 files changed, 10 insertions(+)
-
-diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
-index 25837b1d6639..f11080d63331 100644
---- a/drivers/gpu/drm/drm_fourcc.c
-+++ b/drivers/gpu/drm/drm_fourcc.c
-@@ -261,6 +261,14 @@ const struct drm_format_info *__drm_format_info(u32 format)
- 		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
- 		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
- 		  .vsub = 2, .is_yuv = true },
-+		{ .format = DRM_FORMAT_NV20,		.depth = 0,
-+		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
-+		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
-+		  .vsub = 1, .is_yuv = true },
-+		{ .format = DRM_FORMAT_NV30,		.depth = 0,
-+		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
-+		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1,
-+		  .vsub = 1, .is_yuv = true },
- 		{ .format = DRM_FORMAT_Q410,		.depth = 0,
- 		  .num_planes = 3, .char_per_block = { 2, 2, 2 },
- 		  .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
-diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
-index 7f652c96845b..37824734633c 100644
---- a/include/uapi/drm/drm_fourcc.h
-+++ b/include/uapi/drm/drm_fourcc.h
-@@ -285,6 +285,8 @@ extern "C" {
-  * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
-  */
- #define DRM_FORMAT_NV15		fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
-+#define DRM_FORMAT_NV20		fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
-+#define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
- 
- /*
-  * 2 plane YCbCr MSB aligned
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 6 Jul 2020 22:30:13 +0000
-Subject: [PATCH] drm: rockchip: add NV15, NV20 and NV30 support
-
-Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the
-Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
-Also add support for 10-bit 4:4:4 format while at it.
-
-V2: Added NV30 support
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Reviewed-by: Sandy Huang <hjc@rock-chips.com>
----
- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++--
- drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  1 +
- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 32 +++++++++++++++++----
- 3 files changed, 54 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-index a25b98b7f5bd..91ded8a096ba 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-@@ -262,6 +262,18 @@ static bool has_rb_swapped(uint32_t format)
- 	}
- }
- 
-+static bool is_fmt_10(uint32_t format)
-+{
-+	switch (format) {
-+	case DRM_FORMAT_NV15:
-+	case DRM_FORMAT_NV20:
-+	case DRM_FORMAT_NV30:
-+		return true;
-+	default:
-+		return false;
-+	}
-+}
-+
- static enum vop_data_format vop_convert_format(uint32_t format)
- {
- 	switch (format) {
-@@ -277,10 +289,13 @@ static enum vop_data_format vop_convert_format(uint32_t format)
- 	case DRM_FORMAT_BGR565:
- 		return VOP_FMT_RGB565;
- 	case DRM_FORMAT_NV12:
-+	case DRM_FORMAT_NV15:
- 		return VOP_FMT_YUV420SP;
- 	case DRM_FORMAT_NV16:
-+	case DRM_FORMAT_NV20:
- 		return VOP_FMT_YUV422SP;
- 	case DRM_FORMAT_NV24:
-+	case DRM_FORMAT_NV30:
- 		return VOP_FMT_YUV444SP;
- 	default:
- 		DRM_ERROR("unsupported format[%08x]\n", format);
-@@ -931,7 +946,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
- 	dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
- 	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
- 
--	offset = (src->x1 >> 16) * fb->format->cpp[0];
-+	if (fb->format->block_w[0])
-+		offset = (src->x1 >> 16) * fb->format->char_per_block[0] /
-+			 fb->format->block_w[0];
-+	else
-+		offset = (src->x1 >> 16) * fb->format->cpp[0];
-+
- 	offset += (src->y1 >> 16) * fb->pitches[0];
- 	dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
- 
-@@ -957,6 +977,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
- 	}
- 
- 	VOP_WIN_SET(vop, win, format, format);
-+	VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
- 	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
- 	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
- 	VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
-@@ -973,7 +994,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
- 		uv_obj = fb->obj[1];
- 		rk_uv_obj = to_rockchip_obj(uv_obj);
- 
--		offset = (src->x1 >> 16) * bpp / hsub;
-+		if (fb->format->block_w[1])
-+			offset = (src->x1 >> 16) * bpp /
-+				 fb->format->block_w[1] / hsub;
-+		else
-+			offset = (src->x1 >> 16) * bpp / hsub;
- 		offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
- 
- 		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-index 857d97cdc67c..b7169010622a 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-@@ -165,6 +165,7 @@ struct vop_win_phy {
- 	struct vop_reg enable;
- 	struct vop_reg gate;
- 	struct vop_reg format;
-+	struct vop_reg fmt_10;
- 	struct vop_reg rb_swap;
- 	struct vop_reg act_info;
- 	struct vop_reg dsp_info;
-diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-index 1f7353f0684a..474cc8807ac9 100644
---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-@@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = {
- 	DRM_FORMAT_NV24,
- };
- 
-+static const uint32_t formats_win_full_10[] = {
-+	DRM_FORMAT_XRGB8888,
-+	DRM_FORMAT_ARGB8888,
-+	DRM_FORMAT_XBGR8888,
-+	DRM_FORMAT_ABGR8888,
-+	DRM_FORMAT_RGB888,
-+	DRM_FORMAT_BGR888,
-+	DRM_FORMAT_RGB565,
-+	DRM_FORMAT_BGR565,
-+	DRM_FORMAT_NV12,
-+	DRM_FORMAT_NV16,
-+	DRM_FORMAT_NV24,
-+	DRM_FORMAT_NV15,
-+	DRM_FORMAT_NV20,
-+	DRM_FORMAT_NV30,
-+};
-+
- static const uint64_t format_modifiers_win_full[] = {
- 	DRM_FORMAT_MOD_LINEAR,
- 	DRM_FORMAT_MOD_INVALID,
-@@ -613,11 +630,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = {
- 
- static const struct vop_win_phy rk3288_win01_data = {
- 	.scl = &rk3288_win_full_scl,
--	.data_formats = formats_win_full,
--	.nformats = ARRAY_SIZE(formats_win_full),
-+	.data_formats = formats_win_full_10,
-+	.nformats = ARRAY_SIZE(formats_win_full_10),
- 	.format_modifiers = format_modifiers_win_full,
- 	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
- 	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
-+	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
- 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
- 	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
- 	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
-@@ -747,11 +765,12 @@ static const struct vop_intr rk3368_vop_intr = {
- 
- static const struct vop_win_phy rk3368_win01_data = {
- 	.scl = &rk3288_win_full_scl,
--	.data_formats = formats_win_full,
--	.nformats = ARRAY_SIZE(formats_win_full),
-+	.data_formats = formats_win_full_10,
-+	.nformats = ARRAY_SIZE(formats_win_full_10),
- 	.format_modifiers = format_modifiers_win_full,
- 	.enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
- 	.format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
-+	.fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4),
- 	.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
- 	.x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
- 	.y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
-@@ -896,11 +915,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
- 
- static const struct vop_win_phy rk3399_win01_data = {
- 	.scl = &rk3288_win_full_scl,
--	.data_formats = formats_win_full,
--	.nformats = ARRAY_SIZE(formats_win_full),
-+	.data_formats = formats_win_full_10,
-+	.nformats = ARRAY_SIZE(formats_win_full_10),
- 	.format_modifiers = format_modifiers_win_full_afbc,
- 	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
- 	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
-+	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
- 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
- 	.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
- 	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Qinglang Miao <miaoqinglang@huawei.com>
-Date: Tue, 1 Dec 2020 20:54:57 +0800
-Subject: [PATCH] drm/rockchip: cdn-dp: fix reference leak when
- pm_runtime_get_sync fails
-
-The PM reference count is not expected to be incremented on
-return in cdn_dp_clk_enable.
-
-However, pm_runtime_get_sync will increment the PM reference
-count even failed. Forgetting to putting operation will result
-in a reference leak here.
-
-Replace it with pm_runtime_resume_and_get to keep usage
-counter balanced.
-
-Fixes: efe0220fc2d2 ("drm/rockchip: cdn-dp: Fix error handling")
-Reported-by: Hulk Robot <hulkci@huawei.com>
-Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
----
- drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
-index 16497c31d9f9..e46963577854 100644
---- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
-+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
-@@ -100,7 +100,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp)
- 		goto err_core_clk;
- 	}
- 
--	ret = pm_runtime_get_sync(dp->dev);
-+	ret = pm_runtime_resume_and_get(dp->dev);
- 	if (ret < 0) {
- 		DRM_DEV_ERROR(dp->dev, "cannot get pm runtime %d\n", ret);
- 		goto err_pm_runtime_get;
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Qinglang Miao <miaoqinglang@huawei.com>
-Date: Tue, 1 Dec 2020 20:54:58 +0800
-Subject: [PATCH] drm/rockchip: vop: fix reference leak when
- pm_runtime_get_sync fails
-
-The PM reference count is not expected to be incremented on
-return in functions vop_enable and vop_enable.
-
-However, pm_runtime_get_sync will increment the PM reference
-count even failed. Forgetting to putting operation will result
-in a reference leak here.
-
-Replace it with pm_runtime_resume_and_get to keep usage
-counter balanced.
-
-Fixes: 5e570373c015 ("drm/rockchip: vop: Enable pm domain before vop_initial")
-Reported-by: Hulk Robot <hulkci@huawei.com>
-Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
----
- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-index 91ded8a096ba..967f29625d7c 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-@@ -603,7 +603,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
- 	struct vop *vop = to_vop(crtc);
- 	int ret, i;
- 
--	ret = pm_runtime_get_sync(vop->dev);
-+	ret = pm_runtime_resume_and_get(vop->dev);
- 	if (ret < 0) {
- 		DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
- 		return ret;
-@@ -1953,7 +1953,7 @@ static int vop_initial(struct vop *vop)
- 		return PTR_ERR(vop->dclk);
- 	}
- 
--	ret = pm_runtime_get_sync(vop->dev);
-+	ret = pm_runtime_resume_and_get(vop->dev);
- 	if (ret < 0) {
- 		DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
- 		return ret;
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Qinglang Miao <miaoqinglang@huawei.com>
-Date: Tue, 1 Dec 2020 20:54:59 +0800
-Subject: [PATCH] drm/rockchip: lvds: fix reference leak when
- pm_runtime_get_sync fails
-
-The PM reference count is not expected to be incremented on
-return in functions rk3288_lvds_poweron and px30_lvds_poweron.
-
-However, pm_runtime_get_sync will increment the PM reference
-count even failed. Forgetting to putting operation will result
-in a reference leak here.
-
-Replace it with pm_runtime_resume_and_get to keep usage
-counter balanced.
-
-Fixes: cca1705c3d89 ("drm/rockchip: lvds: Add PX30 support")
-Reported-by: Hulk Robot <hulkci@huawei.com>
-Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
----
- drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c
-index be74c87a8be4..288462fd5d8e 100644
---- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
-@@ -146,7 +146,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds)
- 		DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret);
- 		return ret;
- 	}
--	ret = pm_runtime_get_sync(lvds->dev);
-+	ret = pm_runtime_resume_and_get(lvds->dev);
- 	if (ret < 0) {
- 		DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
- 		clk_disable(lvds->pclk);
-@@ -330,7 +330,7 @@ static int px30_lvds_poweron(struct rockchip_lvds *lvds)
- {
- 	int ret;
- 
--	ret = pm_runtime_get_sync(lvds->dev);
-+	ret = pm_runtime_resume_and_get(lvds->dev);
- 	if (ret < 0) {
- 		DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
- 		return ret;
-

patch/kernel/archive/media-5.17/09-linux-1002-for-libreelec.patch

@@ -1,741 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sun, 4 Jul 2021 15:19:44 +0200
-Subject: [PATCH] media: rkvdec: disable QoS for VP9 (corruptions on RK3328
- otherwise)
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++
- drivers/staging/media/rkvdec/rkvdec-vp9.c  | 8 ++++++++
- 2 files changed, 10 insertions(+)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
-index 3acc914888f6..265f5234f4eb 100644
---- a/drivers/staging/media/rkvdec/rkvdec-regs.h
-+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
-@@ -222,6 +222,8 @@
- #define RKVDEC_REG_H264_ERR_E				0x134
- #define RKVDEC_H264_ERR_EN_HIGHBITS(x)			((x) & 0x3fffffff)
- 
-+#define RKVDEC_QOS_CTRL					0x18C
-+
- #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND		0x410
- #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND		0x450
- 
-diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c
-index 311a12656072..ea270262bbed 100644
---- a/drivers/staging/media/rkvdec/rkvdec-vp9.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c
-@@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
- 	struct rkvdec_dev *rkvdec = ctx->dev;
- 	struct rkvdec_vp9_run run = { };
- 	int ret;
-+	u32 reg;
- 
- 	ret = rkvdec_vp9_run_preamble(ctx, &run);
- 	if (ret) {
-@@ -823,6 +824,13 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
- 	writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
- 
- 	writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
-+
-+	/* disable QOS for RK3328 - no effect on other SoCs */
-+	reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL);
-+	reg |= 0xFFFF;
-+	reg &= (~BIT(12));
-+	writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL);
-+
- 	/* Start decoding! */
- 	writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
- 	       RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Wed, 2 Sep 2020 19:52:02 +0200
-Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and
- cooling cell for RK3328
-
-Note: since the regulator that supplies the GPU usually also supplies
-other SoC components, we have to make sure voltage is never lower then
-1050 mV - also disable 500 MHz for now, since it will crash if rkvdec
-is running at the same time (voltage to high)
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 ++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-index d8a812a7d23b..e4c6a33b4b7e 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -300,6 +300,11 @@ power: power-controller {
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 
-+			power-domain@RK3328_PD_GPU {
-+				reg = <RK3328_PD_GPU>;
-+				clocks = <&cru ACLK_GPU>;
-+				#power-domain-cells = <0>;
-+			};
- 			power-domain@RK3328_PD_HEVC {
- 				reg = <RK3328_PD_HEVC>;
- 				#power-domain-cells = <0>;
-@@ -539,6 +544,11 @@ map0 {
- 							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- 					contribution = <4096>;
- 				};
-+				map1 {
-+					trip = <&target>;
-+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+					contribution = <4096>;
-+				};
- 			};
- 		};
- 
-@@ -620,7 +630,32 @@ gpu: gpu@ff300000 {
- 				  "ppmmu1";
- 		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
- 		clock-names = "bus", "core";
-+		operating-points-v2 = <&gpu_opp_table>;
-+		power-domains = <&power RK3328_PD_GPU>;
- 		resets = <&cru SRST_GPU_A>;
-+		#cooling-cells = <2>;
-+	};
-+
-+	gpu_opp_table: gpu-opp-table {
-+		compatible = "operating-points-v2";
-+
-+		opp-200000000 {
-+			opp-hz = /bits/ 64 <200000000>;
-+			opp-microvolt = <1050000>;
-+		};
-+		opp-300000000 {
-+			opp-hz = /bits/ 64 <300000000>;
-+			opp-microvolt = <1050000>;
-+		};
-+		opp-400000000 {
-+			opp-hz = /bits/ 64 <400000000>;
-+			opp-microvolt = <1050000>;
-+		};
-+		opp-500000000 {
-+			opp-hz = /bits/ 64 <500000000>;
-+			opp-microvolt = <1150000>;
-+			status = "disabled";
-+		};
- 	};
- 
- 	h265e_mmu: iommu@ff330200 {
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Tue, 2 Feb 2021 17:22:21 +0200
-Subject: [PATCH] ARM: dts: RK3288 miqi add hdmi sound nodes
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm/boot/dts/rk3288-miqi.dts | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
-index 713f55e143c6..8d30c49f406e 100644
---- a/arch/arm/boot/dts/rk3288-miqi.dts
-+++ b/arch/arm/boot/dts/rk3288-miqi.dts
-@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator {
- 		regulator-always-on;
- 		regulator-boot-on;
- 	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,format = "i2s";
-+		simple-audio-card,name = "HDMI";
-+		simple-audio-card,mclk-fs = <512>;
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&hdmi>;
-+		};
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&i2s>;
-+		};
-+	};
- };
- 
- &cpu0 {
-@@ -284,6 +299,11 @@ &i2c5 {
- 	status = "okay";
- };
- 
-+&i2s {
-+	#sound-dai-cells = <0>;
-+	status = "okay";
-+};
-+
- &io_domains {
- 	status = "okay";
- 
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Fri, 2 Apr 2021 17:54:22 +0200
-Subject: [PATCH] ARM/arm64: dts: rockchip: align sound card names
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm/boot/dts/rk3288-tinker.dtsi     | 2 +-
- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
-index 9c1e38c54eae..ee332fc9cf1f 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dtsi
-+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
-@@ -75,7 +75,7 @@ sdio_pwrseq: sdio-pwrseq {
- 	sound {
- 		compatible = "simple-audio-card";
- 		simple-audio-card,format = "i2s";
--		simple-audio-card,name = "rockchip,tinker-codec";
-+		simple-audio-card,name = "HDMI";
- 		simple-audio-card,mclk-fs = <512>;
- 
- 		simple-audio-card,codec {
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index 533a031c7e24..c4894053b3f6 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1867,7 +1867,7 @@ hdmi_sound: hdmi-sound {
- 		compatible = "simple-audio-card";
- 		simple-audio-card,format = "i2s";
- 		simple-audio-card,mclk-fs = <256>;
--		simple-audio-card,name = "hdmi-sound";
-+		simple-audio-card,name = "HDMI";
- 		status = "disabled";
- 
- 		simple-audio-card,cpu {
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Wed, 10 Feb 2021 18:44:56 +0200
-Subject: [PATCH] HACK: drm/gem: suppress warning about missing vm_flags
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/gpu/drm/drm_gem.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
-index 4dcdec6487bb..6549651b9978 100644
---- a/drivers/gpu/drm/drm_gem.c
-+++ b/drivers/gpu/drm/drm_gem.c
-@@ -1051,7 +1051,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
- 		ret = obj->funcs->mmap(obj, vma);
- 		if (ret)
- 			goto err_drm_gem_object_put;
--		WARN_ON(!(vma->vm_flags & VM_DONTEXPAND));
-+		//WARN_ON(!(vma->vm_flags & VM_DONTEXPAND));
- 	} else {
- 		if (!vma->vm_ops) {
- 			ret = -EINVAL;
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sun, 25 Mar 2018 22:17:06 +0200
-Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation
-
----
- sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------
- 1 file changed, 52 insertions(+), 61 deletions(-)
-
-diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
-index b61f980cabdc..3ad50ae8c93d 100644
---- a/sound/soc/codecs/hdmi-codec.c
-+++ b/sound/soc/codecs/hdmi-codec.c
-@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
-  */
- static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
- 	{ .ca_id = 0x00, .n_ch = 2,
--	  .mask = FL | FR},
--	/* 2.1 */
--	{ .ca_id = 0x01, .n_ch = 4,
--	  .mask = FL | FR | LFE},
--	/* Dolby Surround */
-+	  .mask = FL | FR },
-+	{ .ca_id = 0x03, .n_ch = 4,
-+	  .mask = FL | FR | LFE | FC },
- 	{ .ca_id = 0x02, .n_ch = 4,
- 	  .mask = FL | FR | FC },
--	/* surround51 */
-+	{ .ca_id = 0x01, .n_ch = 4,
-+	  .mask = FL | FR | LFE },
- 	{ .ca_id = 0x0b, .n_ch = 6,
--	  .mask = FL | FR | LFE | FC | RL | RR},
--	/* surround40 */
--	{ .ca_id = 0x08, .n_ch = 6,
--	  .mask = FL | FR | RL | RR },
--	/* surround41 */
--	{ .ca_id = 0x09, .n_ch = 6,
--	  .mask = FL | FR | LFE | RL | RR },
--	/* surround50 */
-+	  .mask = FL | FR | LFE | FC | RL | RR },
- 	{ .ca_id = 0x0a, .n_ch = 6,
- 	  .mask = FL | FR | FC | RL | RR },
--	/* 6.1 */
--	{ .ca_id = 0x0f, .n_ch = 8,
--	  .mask = FL | FR | LFE | FC | RL | RR | RC },
--	/* surround71 */
-+	{ .ca_id = 0x09, .n_ch = 6,
-+	  .mask = FL | FR | LFE | RL | RR },
-+	{ .ca_id = 0x08, .n_ch = 6,
-+	  .mask = FL | FR | RL | RR },
-+	{ .ca_id = 0x07, .n_ch = 6,
-+	  .mask = FL | FR | LFE | FC | RC },
-+	{ .ca_id = 0x06, .n_ch = 6,
-+	  .mask = FL | FR | FC | RC },
-+	{ .ca_id = 0x05, .n_ch = 6,
-+	  .mask = FL | FR | LFE | RC },
-+	{ .ca_id = 0x04, .n_ch = 6,
-+	  .mask = FL | FR | RC },
- 	{ .ca_id = 0x13, .n_ch = 8,
- 	  .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
--	/* others */
--	{ .ca_id = 0x03, .n_ch = 8,
--	  .mask = FL | FR | LFE | FC },
--	{ .ca_id = 0x04, .n_ch = 8,
--	  .mask = FL | FR | RC},
--	{ .ca_id = 0x05, .n_ch = 8,
--	  .mask = FL | FR | LFE | RC },
--	{ .ca_id = 0x06, .n_ch = 8,
--	  .mask = FL | FR | FC | RC },
--	{ .ca_id = 0x07, .n_ch = 8,
--	  .mask = FL | FR | LFE | FC | RC },
--	{ .ca_id = 0x0c, .n_ch = 8,
--	  .mask = FL | FR | RC | RL | RR },
--	{ .ca_id = 0x0d, .n_ch = 8,
--	  .mask = FL | FR | LFE | RL | RR | RC },
--	{ .ca_id = 0x0e, .n_ch = 8,
--	  .mask = FL | FR | FC | RL | RR | RC },
--	{ .ca_id = 0x10, .n_ch = 8,
--	  .mask = FL | FR | RL | RR | RLC | RRC },
--	{ .ca_id = 0x11, .n_ch = 8,
--	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
-+	{ .ca_id = 0x1f, .n_ch = 8,
-+	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
- 	{ .ca_id = 0x12, .n_ch = 8,
- 	  .mask = FL | FR | FC | RL | RR | RLC | RRC },
--	{ .ca_id = 0x14, .n_ch = 8,
--	  .mask = FL | FR | FLC | FRC },
--	{ .ca_id = 0x15, .n_ch = 8,
--	  .mask = FL | FR | LFE | FLC | FRC },
--	{ .ca_id = 0x16, .n_ch = 8,
--	  .mask = FL | FR | FC | FLC | FRC },
--	{ .ca_id = 0x17, .n_ch = 8,
--	  .mask = FL | FR | LFE | FC | FLC | FRC },
--	{ .ca_id = 0x18, .n_ch = 8,
--	  .mask = FL | FR | RC | FLC | FRC },
--	{ .ca_id = 0x19, .n_ch = 8,
--	  .mask = FL | FR | LFE | RC | FLC | FRC },
--	{ .ca_id = 0x1a, .n_ch = 8,
--	  .mask = FL | FR | RC | FC | FLC | FRC },
--	{ .ca_id = 0x1b, .n_ch = 8,
--	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
--	{ .ca_id = 0x1c, .n_ch = 8,
--	  .mask = FL | FR | RL | RR | FLC | FRC },
--	{ .ca_id = 0x1d, .n_ch = 8,
--	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
- 	{ .ca_id = 0x1e, .n_ch = 8,
- 	  .mask = FL | FR | FC | RL | RR | FLC | FRC },
--	{ .ca_id = 0x1f, .n_ch = 8,
--	  .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
-+	{ .ca_id = 0x11, .n_ch = 8,
-+	  .mask = FL | FR | LFE | RL | RR | RLC | RRC },
-+	{ .ca_id = 0x1d, .n_ch = 8,
-+	  .mask = FL | FR | LFE | RL | RR | FLC | FRC },
-+	{ .ca_id = 0x10, .n_ch = 8,
-+	  .mask = FL | FR | RL | RR | RLC | RRC },
-+	{ .ca_id = 0x1c, .n_ch = 8,
-+	  .mask = FL | FR | RL | RR | FLC | FRC },
-+	{ .ca_id = 0x0f, .n_ch = 8,
-+	  .mask = FL | FR | LFE | FC | RL | RR | RC },
-+	{ .ca_id = 0x1b, .n_ch = 8,
-+	  .mask = FL | FR | LFE | RC | FC | FLC | FRC },
-+	{ .ca_id = 0x0e, .n_ch = 8,
-+	  .mask = FL | FR | FC | RL | RR | RC },
-+	{ .ca_id = 0x1a, .n_ch = 8,
-+	  .mask = FL | FR | RC | FC | FLC | FRC },
-+	{ .ca_id = 0x0d, .n_ch = 8,
-+	  .mask = FL | FR | LFE | RL | RR | RC },
-+	{ .ca_id = 0x19, .n_ch = 8,
-+	  .mask = FL | FR | LFE | RC | FLC | FRC },
-+	{ .ca_id = 0x0c, .n_ch = 8,
-+	  .mask = FL | FR | RC | RL | RR },
-+	{ .ca_id = 0x18, .n_ch = 8,
-+	  .mask = FL | FR | RC | FLC | FRC },
-+	{ .ca_id = 0x17, .n_ch = 8,
-+	  .mask = FL | FR | LFE | FC | FLC | FRC },
-+	{ .ca_id = 0x16, .n_ch = 8,
-+	  .mask = FL | FR | FC | FLC | FRC },
-+	{ .ca_id = 0x15, .n_ch = 8,
-+	  .mask = FL | FR | LFE | FLC | FRC },
-+	{ .ca_id = 0x14, .n_ch = 8,
-+	  .mask = FL | FR | FLC | FRC },
- };
- 
- struct hdmi_codec_priv {
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sun, 2 May 2021 20:44:21 +0200
-Subject: [PATCH] arm64: dts: rockchip: Fix gmac delays for rockpro64 board
-
-Values are measured by RK's delayline tool in vendor kernel
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-index 83db4ca67334..06d2a1e3e340 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-@@ -289,8 +289,8 @@ &gmac {
- 	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- 	snps,reset-active-low;
- 	snps,reset-delays-us = <0 10000 50000>;
--	tx_delay = <0x28>;
--	rx_delay = <0x11>;
-+	tx_delay = <0x23>;
-+	rx_delay = <0x1e>;
- 	status = "okay";
- };
- 
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 27 Feb 2021 17:52:02 +0100
-Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-index de2d3e88e27f..68b74ed080f3 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-@@ -57,6 +57,24 @@ ir-receiver {
- 		gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
- 		linux,rc-map-name = "rc-beelink-gs1";
- 	};
-+
-+	spdif_sound: spdif-sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "SPDIF";
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&spdif>;
-+		};
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&spdif_dit>;
-+		};
-+	};
-+
-+	spdif_dit: spdif-dit {
-+		compatible = "linux,spdif-dit";
-+		#sound-dai-cells = <0>;
-+	};
- };
- 
- &analog_sound {
-@@ -324,6 +342,11 @@ &sdmmc {
- 	status = "okay";
- };
- 
-+&spdif {
-+	pinctrl-0 = <&spdifm0_tx>;
-+	status = "okay";
-+};
-+
- &tsadc {
- 	rockchip,hw-tshut-mode = <0>;
- 	rockchip,hw-tshut-polarity = <0>;
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 27 Feb 2021 18:01:13 +0100
-Subject: [PATCH] arm64: dts: rockchip: Add ir-receiver node for RK3328 ROC CC
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-index aa22a0c22265..a78fbddd21df 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator {
- 		regulator-boot-on;
- 	};
- 
-+	ir-receiver {
-+		compatible = "gpio-ir-receiver";
-+		gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
-+		pinctrl-0 = <&ir_int>;
-+		pinctrl-names = "default";
-+	};
-+
- 	leds {
- 		compatible = "gpio-leds";
- 
-@@ -308,6 +315,13 @@ &io_domains {
- };
- 
- &pinctrl {
-+
-+	ir {
-+		ir_int: ir-int {
-+			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
- 	pmic {
- 		pmic_int_l: pmic-int-l {
- 			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Mon, 1 Mar 2021 21:24:15 +0100
-Subject: [PATCH] ARM: dts: add cec pinctrl for RK3288 miqi board
-
----
- arch/arm/boot/dts/rk3288-miqi.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
-index 8d30c49f406e..6d90db5a3b75 100644
---- a/arch/arm/boot/dts/rk3288-miqi.dts
-+++ b/arch/arm/boot/dts/rk3288-miqi.dts
-@@ -145,6 +145,8 @@ &gpu {
- 
- &hdmi {
- 	ddc-i2c-bus = <&i2c5>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&hdmi_cec_c0>;
- 	status = "okay";
- };
- 
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Mon, 1 Mar 2021 19:22:15 +0100
-Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also
-
----
- arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-index 68b74ed080f3..6736b5dc53e4 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 {
- 	};
- };
- 
-+&gmac2phy {
-+	clock_in_out = "output";
-+	assigned-clock-rate = <50000000>;
-+	assigned-clocks = <&cru SCLK_MAC2PHY>;
-+	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
-+	status = "okay";
-+};
-+
- &gpu {
- 	mali-supply = <&vdd_logic>;
- };
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Tue, 26 Feb 2019 20:45:14 +0000
-Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error
-
----
- drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++--
- 1 file changed, 16 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
-index c8f44bcb298a..d4280ce4542c 100644
---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
-+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
-@@ -4,6 +4,7 @@
-  *
-  * Copyright (C) 2015-2017 Russell King.
-  */
-+#include <linux/delay.h>
- #include <linux/interrupt.h>
- #include <linux/io.h>
- #include <linux/module.h>
-@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
- 
- 	dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0);
- 
--	if (stat & CEC_STAT_ERROR_INIT) {
--		cec->tx_status = CEC_TX_STATUS_ERROR;
-+	/* Status with both done and error_initiator bits have been seen
-+	 * on Rockchip RK3328 devices, transmit attempt seems to have failed
-+	 * when this happens, report as low drive and block cec-framework
-+	 * 100ms before core retransmits the failed message, this seems to
-+	 * mitigate the issue with failed transmit attempts.
-+	 */
-+	if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) {
-+		pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat);
-+		cec->tx_status = CEC_TX_STATUS_LOW_DRIVE;
- 		cec->tx_done = true;
- 		ret = IRQ_WAKE_THREAD;
- 	} else if (stat & CEC_STAT_DONE) {
-@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
- 		cec->tx_status = CEC_TX_STATUS_NACK;
- 		cec->tx_done = true;
- 		ret = IRQ_WAKE_THREAD;
-+	} else if (stat & CEC_STAT_ERROR_INIT) {
-+		cec->tx_status = CEC_TX_STATUS_ERROR;
-+		cec->tx_done = true;
-+		ret = IRQ_WAKE_THREAD;
- 	}
- 
- 	if (stat & CEC_STAT_EOM) {
-@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data)
- 
- 	if (cec->tx_done) {
- 		cec->tx_done = false;
-+		if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE)
-+			msleep(100);
- 		cec_transmit_attempt_done(adap, cec->tx_status);
- 	}
- 	if (cec->rx_done) {
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Wed, 5 May 2021 19:11:12 +0200
-Subject: [PATCH] arm64: boot: dts: Increase ACLK_PERILP0 clock rate for RK3399
-
-As per vendor kernel. Leaving this clock at the lower rate will
-result in poor DMA controller performance
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index c4894053b3f6..b39a3390bd7d 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1453,7 +1453,7 @@ cru: clock-controller@ff760000 {
- 			<1000000000>,
- 			 <150000000>,   <75000000>,
- 			  <37500000>,
--			 <100000000>,  <100000000>,
-+			 <300000000>,  <100000000>,
- 			  <50000000>, <600000000>,
- 			 <100000000>,   <50000000>,
- 			 <400000000>, <400000000>,
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 21 Aug 2021 17:04:46 +0200
-Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-index 6736b5dc53e4..9000fae2a5ee 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
-@@ -388,6 +388,11 @@ &usb_host0_ehci {
- 	status = "okay";
- };
- 
-+&usbdrd3 {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
- &vop {
- 	status = "okay";
- };
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 21 Aug 2021 14:03:25 +0200
-Subject: [PATCH] HACK: media: hantro: rockchip: disable H264 for RK3328
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/staging/media/hantro/rockchip_vpu_hw.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-index f0014823a093..db4b9fe26256 100644
---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
-+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-@@ -531,8 +531,7 @@ const struct hantro_variant rk3328_vpu_variant = {
- 	.dec_offset = 0x400,
- 	.dec_fmts = rk3399_vpu_dec_fmts,
- 	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
--	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
--		 HANTRO_H264_DECODER,
-+	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
- 	.codec_ops = rk3399_vpu_codec_ops,
- 	.irqs = rockchip_vdpu2_irqs,
- 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 30 Oct 2021 12:19:19 +0200
-Subject: [PATCH] WIP: drm: bridge: dw-hdmi: switch from .hw_parmas to .prepare
- for i2s
-
-Seems to be the only way to get AES bits correctly as set by
-userspace.
-TODO: check other consequences.
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
-index feb04f127b55..f7631f2e34c5 100644
---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
-+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
-@@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset)
- 	return audio->read(hdmi, offset);
- }
- 
--static int dw_hdmi_i2s_hw_params(struct device *dev, void *data,
--				 struct hdmi_codec_daifmt *fmt,
--				 struct hdmi_codec_params *hparms)
-+static int dw_hdmi_i2s_prepare(struct device *dev, void *data,
-+			       struct hdmi_codec_daifmt *fmt,
-+			       struct hdmi_codec_params *hparms)
- {
- 	struct dw_hdmi_i2s_audio_data *audio = data;
- 	struct dw_hdmi *hdmi = audio->hdmi;
-@@ -171,7 +171,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data,
- }
- 
- static const struct hdmi_codec_ops dw_hdmi_i2s_ops = {
--	.hw_params	= dw_hdmi_i2s_hw_params,
-+	.prepare	= dw_hdmi_i2s_prepare,
- 	.audio_startup  = dw_hdmi_i2s_audio_startup,
- 	.audio_shutdown	= dw_hdmi_i2s_audio_shutdown,
- 	.get_eld	= dw_hdmi_i2s_get_eld,

patch/kernel/archive/media-5.17/general-fix-rga-probe.patch

@@ -1,13 +0,0 @@
-diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
-index 6759091b1..d99ea8973 100644
---- a/drivers/media/platform/rockchip/rga/rga.c
-+++ b/drivers/media/platform/rockchip/rga/rga.c
-@@ -895,7 +895,7 @@ static int rga_probe(struct platform_device *pdev)
- 	}
- 	rga->dst_mmu_pages =
- 		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
--	if (rga->dst_mmu_pages) {
-+	if (!rga->dst_mmu_pages) {
- 		ret = -ENOMEM;
- 		goto free_src_pages;
- 	}

patch/kernel/archive/media-5.17/rk3328-add-rga-node.patch

@@ -1,37 +0,0 @@
-From c37d1b1a4ec6f517ba8a8b70d035979c0a9d4966 Mon Sep 17 00:00:00 2001
-From: Paolo Sabatino <paolo.sabatino@gmail.com>
-Date: Thu, 21 Oct 2021 18:04:17 +0000
-Subject: [PATCH] rk3328: add RGA node
-
----
- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-index 162e57936..ecff11781 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -829,6 +829,20 @@ vop_mmu: iommu@ff373f00 {
- 		status = "disabled";
- 	};
- 
-+	rga: rga@ff390000 {
-+		compatible = "rockchip,rk3328-rga", "rockchip,rk3399-rga";
-+		reg = <0x0 0xff390000 0x0 0x1000>;
-+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&cru ACLK_RGA>,
-+			<&cru HCLK_RGA>,
-+			<&cru SCLK_RGA>;
-+		clock-names = "aclk", "hclk", "sclk";
-+		resets = <&cru SRST_RGA>,
-+			<&cru SRST_RGA_A>,
-+			<&cru SRST_RGA_H>;
-+		reset-names = "core", "axi", "ahb";
-+	};
-+
- 	iep: iep@ff3a0000 {
- 		compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep";
- 		reg = <0x0 0xff3a0000 0x0 0x800>;
--- 
-2.30.2
-

patch/kernel/archive/media-5.18/00-v11-01-24-clk-rk3568-Mark-hclk_vo-as-critical.patch

@@ -0,0 +1,12 @@
+diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
+index 606ae6cd918b2..f85902e2590c7 100644
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -1591,6 +1591,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = {
+ 	"hclk_php",
+ 	"pclk_php",
+ 	"hclk_usb",
++	"hclk_vo",
+ };
+ 
+ static const char *const rk3568_pmucru_critical_clocks[] __initconst = {

patch/kernel/archive/media-5.18/00-v11-02-24-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch

@@ -0,0 +1,586 @@
+diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+index c82901d9a9ccd..28fcc8efa33db 100644
+--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
++++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+@@ -40,8 +40,6 @@
+ 
+ #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS	100
+ 
+-#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
+-
+ /**
+  * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
+  * @lcdsel_grf_reg: grf register offset of lcdc select
+@@ -59,7 +57,7 @@ struct rockchip_dp_chip_data {
+ struct rockchip_dp_device {
+ 	struct drm_device        *drm_dev;
+ 	struct device            *dev;
+-	struct drm_encoder       encoder;
++	struct rockchip_encoder  encoder;
+ 	struct drm_display_mode  mode;
+ 
+ 	struct clk               *pclk;
+@@ -73,6 +71,18 @@ struct rockchip_dp_device {
+ 	struct analogix_dp_plat_data plat_data;
+ };
+ 
++static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
++{
++	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++	return container_of(rkencoder, struct rockchip_dp_device, encoder);
++}
++
++static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
++{
++	return container_of(plat_data, struct rockchip_dp_device, plat_data);
++}
++
+ static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+ {
+ 	reset_control_assert(dp->rst);
+@@ -84,7 +94,7 @@ static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+ 
+ static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
+ {
+-	struct rockchip_dp_device *dp = to_dp(plat_data);
++	struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
+ 	int ret;
+ 
+ 	ret = clk_prepare_enable(dp->pclk);
+@@ -105,7 +115,7 @@ static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
+ 
+ static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+ {
+-	struct rockchip_dp_device *dp = to_dp(plat_data);
++	struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
+ 
+ 	clk_disable_unprepare(dp->pclk);
+ 
+@@ -166,7 +176,7 @@ struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
+ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
+ 					   struct drm_atomic_state *state)
+ {
+-	struct rockchip_dp_device *dp = to_dp(encoder);
++	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+ 	struct drm_crtc *crtc;
+ 	struct drm_crtc_state *old_crtc_state;
+ 	int ret;
+@@ -208,7 +218,7 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
+ static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
+ 					    struct drm_atomic_state *state)
+ {
+-	struct rockchip_dp_device *dp = to_dp(encoder);
++	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+ 	struct drm_crtc *crtc;
+ 	struct drm_crtc_state *new_crtc_state = NULL;
+ 	int ret;
+@@ -297,7 +307,7 @@ static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
+ 
+ static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+ {
+-	struct drm_encoder *encoder = &dp->encoder;
++	struct drm_encoder *encoder = &dp->encoder.encoder;
+ 	struct drm_device *drm_dev = dp->drm_dev;
+ 	struct device *dev = dp->dev;
+ 	int ret;
+@@ -333,7 +343,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
+ 		return ret;
+ 	}
+ 
+-	dp->plat_data.encoder = &dp->encoder;
++	dp->plat_data.encoder = &dp->encoder.encoder;
+ 
+ 	ret = analogix_dp_bind(dp->adp, drm_dev);
+ 	if (ret)
+@@ -341,7 +351,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
+ 
+ 	return 0;
+ err_cleanup_encoder:
+-	dp->encoder.funcs->destroy(&dp->encoder);
++	dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
+ 	return ret;
+ }
+ 
+@@ -351,7 +361,7 @@ static void rockchip_dp_unbind(struct device *dev, struct device *master,
+ 	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+ 
+ 	analogix_dp_unbind(dp->adp);
+-	dp->encoder.funcs->destroy(&dp->encoder);
++	dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
+ }
+ 
+ static const struct component_ops rockchip_dp_component_ops = {
+diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
+index d3e6c93739bf6..8584e19792be2 100644
+--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
+@@ -26,11 +26,17 @@
+ #include "cdn-dp-reg.h"
+ #include "rockchip_drm_vop.h"
+ 
+-#define connector_to_dp(c) \
+-		container_of(c, struct cdn_dp_device, connector)
++static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector)
++{
++	return container_of(connector, struct cdn_dp_device, connector);
++}
+ 
+-#define encoder_to_dp(c) \
+-		container_of(c, struct cdn_dp_device, encoder)
++static inline struct cdn_dp_device *encoder_to_dp(struct drm_encoder *encoder)
++{
++	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++	return container_of(rkencoder, struct cdn_dp_device, encoder);
++}
+ 
+ #define GRF_SOC_CON9		0x6224
+ #define DP_SEL_VOP_LIT		BIT(12)
+@@ -1050,7 +1056,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data)
+ 
+ 	INIT_WORK(&dp->event_work, cdn_dp_pd_event_work);
+ 
+-	encoder = &dp->encoder;
++	encoder = &dp->encoder.encoder;
+ 
+ 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+ 							     dev->of_node);
+@@ -1115,7 +1121,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data)
+ static void cdn_dp_unbind(struct device *dev, struct device *master, void *data)
+ {
+ 	struct cdn_dp_device *dp = dev_get_drvdata(dev);
+-	struct drm_encoder *encoder = &dp->encoder;
++	struct drm_encoder *encoder = &dp->encoder.encoder;
+ 	struct drm_connector *connector = &dp->connector;
+ 
+ 	cancel_work_sync(&dp->event_work);
+diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h
+index 6d0c5032ef3ad..f7d4cecb46ba4 100644
+--- a/drivers/gpu/drm/rockchip/cdn-dp-core.h
++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h
+@@ -66,7 +66,7 @@ struct cdn_dp_device {
+ 	struct device *dev;
+ 	struct drm_device *drm_dev;
+ 	struct drm_connector connector;
+-	struct drm_encoder encoder;
++	struct rockchip_encoder encoder;
+ 	struct drm_display_mode mode;
+ 	struct platform_device *audio_pdev;
+ 	struct work_struct event_work;
+diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+index 4ed7a68681978..110e83aad9bb4 100644
+--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+@@ -181,8 +181,6 @@
+ 
+ #define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)
+ 
+-#define to_dsi(nm)	container_of(nm, struct dw_mipi_dsi_rockchip, nm)
+-
+ enum {
+ 	DW_DSI_USAGE_IDLE,
+ 	DW_DSI_USAGE_DSI,
+@@ -236,7 +234,7 @@ struct rockchip_dw_dsi_chip_data {
+ 
+ struct dw_mipi_dsi_rockchip {
+ 	struct device *dev;
+-	struct drm_encoder encoder;
++	struct rockchip_encoder encoder;
+ 	void __iomem *base;
+ 
+ 	struct regmap *grf_regmap;
+@@ -271,6 +269,13 @@ struct dw_mipi_dsi_rockchip {
+ 	bool dsi_bound;
+ };
+ 
++static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder)
++{
++	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++	return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder);
++}
++
+ struct dphy_pll_parameter_map {
+ 	unsigned int max_mbps;
+ 	u8 hsfreqrange;
+@@ -770,7 +775,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	int ret, mux;
+ 
+ 	mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
+-						&dsi->encoder);
++						&dsi->encoder.encoder);
+ 	if (mux < 0)
+ 		return;
+ 
+@@ -801,7 +806,7 @@ dw_mipi_dsi_encoder_helper_funcs = {
+ static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
+ 					   struct drm_device *drm_dev)
+ {
+-	struct drm_encoder *encoder = &dsi->encoder;
++	struct drm_encoder *encoder = &dsi->encoder.encoder;
+ 	int ret;
+ 
+ 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+@@ -959,7 +964,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
+ 		goto out_pll_clk;
+ 	}
+ 
+-	ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
++	ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
+ 	if (ret) {
+ 		DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
+ 		goto out_pll_clk;
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 8677c82716784..06c9ddef6f362 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -67,7 +67,7 @@ struct rockchip_hdmi_chip_data {
+ struct rockchip_hdmi {
+ 	struct device *dev;
+ 	struct regmap *regmap;
+-	struct drm_encoder encoder;
++	struct rockchip_encoder encoder;
+ 	const struct rockchip_hdmi_chip_data *chip_data;
+ 	struct clk *vpll_clk;
+ 	struct clk *grf_clk;
+@@ -75,7 +75,12 @@ struct rockchip_hdmi {
+ 	struct phy *phy;
+ };
+ 
+-#define to_rockchip_hdmi(x)	container_of(x, struct rockchip_hdmi, x)
++static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
++{
++	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++	return container_of(rkencoder, struct rockchip_hdmi, encoder);
++}
+ 
+ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	{
+@@ -511,7 +516,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	hdmi->dev = &pdev->dev;
+ 	hdmi->chip_data = plat_data->phy_data;
+ 	plat_data->phy_data = hdmi;
+-	encoder = &hdmi->encoder;
++	encoder = &hdmi->encoder.encoder;
+ 
+ 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
+ 	/*
+diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c
+index 046e8ec2a71c5..0a4f72021d6af 100644
+--- a/drivers/gpu/drm/rockchip/inno_hdmi.c
++++ b/drivers/gpu/drm/rockchip/inno_hdmi.c
+@@ -26,8 +26,6 @@
+ 
+ #include "inno_hdmi.h"
+ 
+-#define to_inno_hdmi(x)	container_of(x, struct inno_hdmi, x)
+-
+ struct hdmi_data_info {
+ 	int vic;
+ 	bool sink_is_hdmi;
+@@ -56,7 +54,7 @@ struct inno_hdmi {
+ 	void __iomem *regs;
+ 
+ 	struct drm_connector	connector;
+-	struct drm_encoder	encoder;
++	struct rockchip_encoder	encoder;
+ 
+ 	struct inno_hdmi_i2c *i2c;
+ 	struct i2c_adapter *ddc;
+@@ -67,6 +65,18 @@ struct inno_hdmi {
+ 	struct drm_display_mode previous_mode;
+ };
+ 
++static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder)
++{
++	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++	return container_of(rkencoder, struct inno_hdmi, encoder);
++}
++
++static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
++{
++	return container_of(connector, struct inno_hdmi, connector);
++}
++
+ enum {
+ 	CSC_ITU601_16_235_TO_RGB_0_255_8BIT,
+ 	CSC_ITU601_0_255_TO_RGB_0_255_8BIT,
+@@ -483,7 +493,7 @@ static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ 				       struct drm_display_mode *mode,
+ 				       struct drm_display_mode *adj_mode)
+ {
+-	struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
++	struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
+ 
+ 	inno_hdmi_setup(hdmi, adj_mode);
+ 
+@@ -493,14 +503,14 @@ static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ 
+ static void inno_hdmi_encoder_enable(struct drm_encoder *encoder)
+ {
+-	struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
++	struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
+ 
+ 	inno_hdmi_set_pwr_mode(hdmi, NORMAL);
+ }
+ 
+ static void inno_hdmi_encoder_disable(struct drm_encoder *encoder)
+ {
+-	struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
++	struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
+ 
+ 	inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR);
+ }
+@@ -536,7 +546,7 @@ static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
+ static enum drm_connector_status
+ inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
+ {
+-	struct inno_hdmi *hdmi = to_inno_hdmi(connector);
++	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
+ 
+ 	return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
+ 		connector_status_connected : connector_status_disconnected;
+@@ -544,7 +554,7 @@ inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
+ 
+ static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
+ {
+-	struct inno_hdmi *hdmi = to_inno_hdmi(connector);
++	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
+ 	struct edid *edid;
+ 	int ret = 0;
+ 
+@@ -599,7 +609,7 @@ static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
+ 
+ static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
+ {
+-	struct drm_encoder *encoder = &hdmi->encoder;
++	struct drm_encoder *encoder = &hdmi->encoder.encoder;
+ 	struct device *dev = hdmi->dev;
+ 
+ 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
+@@ -879,7 +889,7 @@ static int inno_hdmi_bind(struct device *dev, struct device *master,
+ 	return 0;
+ err_cleanup_hdmi:
+ 	hdmi->connector.funcs->destroy(&hdmi->connector);
+-	hdmi->encoder.funcs->destroy(&hdmi->encoder);
++	hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
+ err_put_adapter:
+ 	i2c_put_adapter(hdmi->ddc);
+ err_disable_clk:
+@@ -893,7 +903,7 @@ static void inno_hdmi_unbind(struct device *dev, struct device *master,
+ 	struct inno_hdmi *hdmi = dev_get_drvdata(dev);
+ 
+ 	hdmi->connector.funcs->destroy(&hdmi->connector);
+-	hdmi->encoder.funcs->destroy(&hdmi->encoder);
++	hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
+ 
+ 	i2c_put_adapter(hdmi->ddc);
+ 	clk_disable_unprepare(hdmi->pclk);
+diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
+index 1c546c3a89984..319240c33dcc0 100644
+--- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c
++++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
+@@ -47,7 +47,7 @@ struct rk3066_hdmi {
+ 	void __iomem *regs;
+ 
+ 	struct drm_connector connector;
+-	struct drm_encoder encoder;
++	struct rockchip_encoder encoder;
+ 
+ 	struct rk3066_hdmi_i2c *i2c;
+ 	struct i2c_adapter *ddc;
+@@ -58,7 +58,17 @@ struct rk3066_hdmi {
+ 	struct drm_display_mode previous_mode;
+ };
+ 
+-#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
++static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder)
++{
++	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++	return container_of(rkencoder, struct rk3066_hdmi, encoder);
++}
++
++static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector)
++{
++	return container_of(connector, struct rk3066_hdmi, connector);
++}
+ 
+ static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
+ {
+@@ -380,7 +390,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ 			     struct drm_display_mode *mode,
+ 			     struct drm_display_mode *adj_mode)
+ {
+-	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
++	struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
+ 
+ 	/* Store the display mode for plugin/DPMS poweron events. */
+ 	memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
+@@ -388,7 +398,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ 
+ static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
+ {
+-	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
++	struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
+ 	int mux, val;
+ 
+ 	mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
+@@ -407,7 +417,7 @@ static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
+ 
+ static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
+ {
+-	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
++	struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
+ 
+ 	DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
+ 
+@@ -455,7 +465,7 @@ struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
+ static enum drm_connector_status
+ rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
+ {
+-	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
++	struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
+ 
+ 	return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
+ 		connector_status_connected : connector_status_disconnected;
+@@ -463,7 +473,7 @@ rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
+ 
+ static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
+ {
+-	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
++	struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
+ 	struct edid *edid;
+ 	int ret = 0;
+ 
+@@ -496,9 +506,9 @@ rk3066_hdmi_connector_mode_valid(struct drm_connector *connector,
+ static struct drm_encoder *
+ rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
+ {
+-	struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
++	struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
+ 
+-	return &hdmi->encoder;
++	return &hdmi->encoder.encoder;
+ }
+ 
+ static int
+@@ -538,7 +548,7 @@ struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = {
+ static int
+ rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
+ {
+-	struct drm_encoder *encoder = &hdmi->encoder;
++	struct drm_encoder *encoder = &hdmi->encoder.encoder;
+ 	struct device *dev = hdmi->dev;
+ 
+ 	encoder->possible_crtcs =
+@@ -816,7 +826,7 @@ static int rk3066_hdmi_bind(struct device *dev, struct device *master,
+ 
+ err_cleanup_hdmi:
+ 	hdmi->connector.funcs->destroy(&hdmi->connector);
+-	hdmi->encoder.funcs->destroy(&hdmi->encoder);
++	hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
+ err_disable_i2c:
+ 	i2c_put_adapter(hdmi->ddc);
+ err_disable_hclk:
+@@ -831,7 +841,7 @@ static void rk3066_hdmi_unbind(struct device *dev, struct device *master,
+ 	struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
+ 
+ 	hdmi->connector.funcs->destroy(&hdmi->connector);
+-	hdmi->encoder.funcs->destroy(&hdmi->encoder);
++	hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
+ 
+ 	i2c_put_adapter(hdmi->ddc);
+ 	clk_disable_unprepare(hdmi->hclk);
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+index 008c44aef4001..048ab277de653 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+@@ -49,6 +49,10 @@ struct rockchip_drm_private {
+ 	struct drm_mm mm;
+ };
+ 
++struct rockchip_encoder {
++	struct drm_encoder encoder;
++};
++
+ int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
+ 				   struct device *dev);
+ void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
+@@ -66,4 +70,10 @@ extern struct platform_driver rockchip_dp_driver;
+ extern struct platform_driver rockchip_lvds_driver;
+ extern struct platform_driver vop_platform_driver;
+ extern struct platform_driver rk3066_hdmi_driver;
++
++static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder)
++{
++	return container_of(encoder, struct rockchip_encoder, encoder);
++}
++
+ #endif /* _ROCKCHIP_DRM_DRV_H_ */
+diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c
+index 0b972418067e8..25d8c24ef7729 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
++++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
+@@ -36,12 +36,6 @@
+ 
+ struct rockchip_lvds;
+ 
+-#define connector_to_lvds(c) \
+-		container_of(c, struct rockchip_lvds, connector)
+-
+-#define encoder_to_lvds(c) \
+-		container_of(c, struct rockchip_lvds, encoder)
+-
+ /**
+  * struct rockchip_lvds_soc_data - rockchip lvds Soc private data
+  * @probe: LVDS platform probe function
+@@ -65,10 +59,22 @@ struct rockchip_lvds {
+ 	struct drm_panel *panel;
+ 	struct drm_bridge *bridge;
+ 	struct drm_connector connector;
+-	struct drm_encoder encoder;
++	struct rockchip_encoder encoder;
+ 	struct dev_pin_info *pins;
+ };
+ 
++static inline struct rockchip_lvds *connector_to_lvds(struct drm_connector *connector)
++{
++	return container_of(connector, struct rockchip_lvds, connector);
++}
++
++static inline struct rockchip_lvds *encoder_to_lvds(struct drm_encoder *encoder)
++{
++	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
++
++	return container_of(rkencoder, struct rockchip_lvds, encoder);
++}
++
+ static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset,
+ 				 u32 val)
+ {
+@@ -599,7 +605,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master,
+ 		goto err_put_remote;
+ 	}
+ 
+-	encoder = &lvds->encoder;
++	encoder = &lvds->encoder.encoder;
+ 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+ 							     dev->of_node);
+ 
+@@ -674,10 +680,10 @@ static void rockchip_lvds_unbind(struct device *dev, struct device *master,
+ 	const struct drm_encoder_helper_funcs *encoder_funcs;
+ 
+ 	encoder_funcs = lvds->soc_data->helper_funcs;
+-	encoder_funcs->disable(&lvds->encoder);
++	encoder_funcs->disable(&lvds->encoder.encoder);
+ 	pm_runtime_disable(dev);
+ 	drm_connector_cleanup(&lvds->connector);
+-	drm_encoder_cleanup(&lvds->encoder);
++	drm_encoder_cleanup(&lvds->encoder.encoder);
+ }
+ 
+ static const struct component_ops rockchip_lvds_component_ops = {

patch/kernel/archive/media-5.18/00-v11-03-24-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch

@@ -0,0 +1,66 @@
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+index 7efd12312354b..0dc09d92d92d6 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+@@ -244,6 +244,39 @@ static const struct dev_pm_ops rockchip_drm_pm_ops = {
+ static struct platform_driver *rockchip_sub_drivers[MAX_ROCKCHIP_SUB_DRIVERS];
+ static int num_rockchip_sub_drivers;
+ 
++/*
++ * Get the endpoint id of the remote endpoint of the given encoder. This
++ * information is used by the VOP2 driver to identify the encoder.
++ *
++ * @rkencoder: The encoder to get the remote endpoint id from
++ * @np: The encoder device node
++ * @port: The number of the port leading to the VOP2
++ * @reg: The endpoint number leading to the VOP2
++ */
++int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rkencoder,
++					      struct device_node *np, int port, int reg)
++{
++	struct of_endpoint ep;
++	struct device_node *en, *ren;
++	int ret;
++
++	en = of_graph_get_endpoint_by_regs(np, port, reg);
++	if (!en)
++		return -ENOENT;
++
++	ren = of_graph_get_remote_endpoint(en);
++	if (!ren)
++		return -ENOENT;
++
++	ret = of_graph_parse_endpoint(ren, &ep);
++	if (ret)
++		return ret;
++
++	rkencoder->crtc_endpoint_id = ep.id;
++
++	return 0;
++}
++
+ /*
+  * Check if a vop endpoint is leading to a rockchip subdriver or bridge.
+  * Should be called from the component bind stage of the drivers
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+index 048ab277de653..a27ab928e1d2f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+@@ -50,6 +50,7 @@ struct rockchip_drm_private {
+ };
+ 
+ struct rockchip_encoder {
++	int crtc_endpoint_id;
+ 	struct drm_encoder encoder;
+ };
+ 
+@@ -60,7 +61,8 @@ void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
+ void rockchip_drm_dma_init_device(struct drm_device *drm_dev,
+ 				  struct device *dev);
+ int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
+-
++int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder,
++					      struct device_node *np, int port, int reg);
+ int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
+ extern struct platform_driver cdn_dp_driver;
+ extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;

patch/kernel/archive/media-5.18/00-v11-04-24-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch

@@ -0,0 +1,75 @@
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 06c9ddef6f362..912181429880a 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -69,7 +69,7 @@ struct rockchip_hdmi {
+ 	struct regmap *regmap;
+ 	struct rockchip_encoder encoder;
+ 	const struct rockchip_hdmi_chip_data *chip_data;
+-	struct clk *vpll_clk;
++	struct clk *ref_clk;
+ 	struct clk *grf_clk;
+ 	struct dw_hdmi *hdmi;
+ 	struct phy *phy;
+@@ -201,14 +201,15 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
+ 		return PTR_ERR(hdmi->regmap);
+ 	}
+ 
+-	hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
+-	if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
+-		hdmi->vpll_clk = NULL;
+-	} else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
++	hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref");
++	if (!hdmi->ref_clk)
++		hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll");
++
++	if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) {
+ 		return -EPROBE_DEFER;
+-	} else if (IS_ERR(hdmi->vpll_clk)) {
+-		DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n");
+-		return PTR_ERR(hdmi->vpll_clk);
++	} else if (IS_ERR(hdmi->ref_clk)) {
++		DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n");
++		return PTR_ERR(hdmi->ref_clk);
+ 	}
+ 
+ 	hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
+@@ -262,7 +263,7 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
+ {
+ 	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ 
+-	clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
++	clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
+ }
+ 
+ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
+@@ -542,9 +543,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 		return ret;
+ 	}
+ 
+-	ret = clk_prepare_enable(hdmi->vpll_clk);
++	ret = clk_prepare_enable(hdmi->ref_clk);
+ 	if (ret) {
+-		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
++		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
+ 			      ret);
+ 		return ret;
+ 	}
+@@ -563,7 +564,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	if (IS_ERR(hdmi->hdmi)) {
+ 		ret = PTR_ERR(hdmi->hdmi);
+ 		drm_encoder_cleanup(encoder);
+-		clk_disable_unprepare(hdmi->vpll_clk);
++		clk_disable_unprepare(hdmi->ref_clk);
+ 	}
+ 
+ 	return ret;
+@@ -575,7 +576,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
+ 	struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
+ 
+ 	dw_hdmi_unbind(hdmi->hdmi);
+-	clk_disable_unprepare(hdmi->vpll_clk);
++	clk_disable_unprepare(hdmi->ref_clk);
+ }
+ 
+ static const struct component_ops dw_hdmi_rockchip_ops = {

patch/kernel/archive/media-5.18/00-v11-05-24-dt-bindings-display-rockchip-dw-hdmi-use-ref-as-clock-name.patch

@@ -0,0 +1,30 @@
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+index da3b889ad8fcd..0400f67e5f2c9 100644
+--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+@@ -36,7 +36,8 @@ properties:
+       # order when present.
+       - description: The HDMI CEC controller main clock
+       - description: Power for GRF IO
+-      - description: External clock for some HDMI PHY
++      - description: External clock for some HDMI PHY (old clock name, deprecated)
++      - description: External clock for some HDMI PHY (new name)
+ 
+   clock-names:
+     minItems: 2
+@@ -47,10 +48,14 @@ properties:
+           - cec
+           - grf
+           - vpll
++          - ref
+       - enum:
+           - grf
+           - vpll
+-      - const: vpll
++          - ref
++      - enum:
++          - vpll
++          - ref
+ 
+   ddc-i2c-bus:
+     $ref: /schemas/types.yaml#/definitions/phandle

patch/kernel/archive/media-5.18/00-v11-06-24-arm64-dts-rockchip-rk3399-rename-HDMI-ref-clock-to-ref.patch

@@ -0,0 +1,13 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 080457a68e3c7..d0add619b0d22 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1884,7 +1884,7 @@ hdmi: hdmi@ff940000 {
+ 			 <&cru SCLK_HDMI_CEC>,
+ 			 <&cru PCLK_VIO_GRF>,
+ 			 <&cru PLL_VPLL>;
+-		clock-names = "iahb", "isfr", "cec", "grf", "vpll";
++		clock-names = "iahb", "isfr", "cec", "grf", "ref";
+ 		power-domains = <&power RK3399_PD_HDCP>;
+ 		reg-io-width = <4>;
+ 		rockchip,grf = <&grf>;

patch/kernel/archive/media-5.18/00-v11-07-24-drm-rockchip-dw_hdmi-add-rk3568-support.patch

@@ -0,0 +1,70 @@
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 912181429880a..b64cc62c7b5af 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -50,6 +50,10 @@
+ #define RK3399_GRF_SOC_CON20		0x6250
+ #define RK3399_HDMI_LCDC_SEL		BIT(6)
+ 
++#define RK3568_GRF_VO_CON1		0x0364
++#define RK3568_HDMI_SDAIN_MSK		BIT(15)
++#define RK3568_HDMI_SCLIN_MSK		BIT(14)
++
+ #define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)
+ 
+ /**
+@@ -473,6 +477,19 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
+ 	.use_drm_infoframe = true,
+ };
+ 
++static struct rockchip_hdmi_chip_data rk3568_chip_data = {
++	.lcdsel_grf_reg = -1,
++};
++
++static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
++	.mode_valid = dw_hdmi_rockchip_mode_valid,
++	.mpll_cfg   = rockchip_mpll_cfg,
++	.cur_ctr    = rockchip_cur_ctr,
++	.phy_config = rockchip_phy_config,
++	.phy_data = &rk3568_chip_data,
++	.use_drm_infoframe = true,
++};
++
+ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
+ 	{ .compatible = "rockchip,rk3228-dw-hdmi",
+ 	  .data = &rk3228_hdmi_drv_data
+@@ -486,6 +503,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
+ 	{ .compatible = "rockchip,rk3399-dw-hdmi",
+ 	  .data = &rk3399_hdmi_drv_data
+ 	},
++	{ .compatible = "rockchip,rk3568-dw-hdmi",
++	  .data = &rk3568_hdmi_drv_data
++	},
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
+@@ -520,6 +540,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	encoder = &hdmi->encoder.encoder;
+ 
+ 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
++	rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
++						  dev->of_node, 0, 0);
++
+ 	/*
+ 	 * If we failed to find the CRTC(s) which this encoder is
+ 	 * supposed to be connected to, it's because the CRTC has
+@@ -550,6 +573,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 		return ret;
+ 	}
+ 
++	if (hdmi->chip_data == &rk3568_chip_data) {
++		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
++			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
++					   RK3568_HDMI_SCLIN_MSK,
++					   RK3568_HDMI_SDAIN_MSK |
++					   RK3568_HDMI_SCLIN_MSK));
++	}
++
+ 	drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
+ 	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
+ 

patch/kernel/archive/media-5.18/00-v11-08-24-dt-bindings-display-rockchip-dw-hdmi-Add-compatible-for-rk3568-HDMI.patch

@@ -0,0 +1,12 @@
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+index 0400f67e5f2c9..e6b8437a1e2d1 100644
+--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+@@ -23,6 +23,7 @@ properties:
+       - rockchip,rk3288-dw-hdmi
+       - rockchip,rk3328-dw-hdmi
+       - rockchip,rk3399-dw-hdmi
++      - rockchip,rk3568-dw-hdmi
+ 
+   reg-io-width:
+     const: 4

patch/kernel/archive/media-5.18/00-v11-09-24-drm-rockchip-dw_hdmi-add-regulator-support.patch

@@ -0,0 +1,93 @@
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index b64cc62c7b5af..fe4f9556239ac 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -9,6 +9,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/phy/phy.h>
+ #include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
+ 
+ #include <drm/bridge/dw_hdmi.h>
+ #include <drm/drm_edid.h>
+@@ -76,6 +77,8 @@ struct rockchip_hdmi {
+ 	struct clk *ref_clk;
+ 	struct clk *grf_clk;
+ 	struct dw_hdmi *hdmi;
++	struct regulator *avdd_0v9;
++	struct regulator *avdd_1v8;
+ 	struct phy *phy;
+ };
+ 
+@@ -226,6 +229,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
+ 		return PTR_ERR(hdmi->grf_clk);
+ 	}
+ 
++	hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
++	if (IS_ERR(hdmi->avdd_0v9))
++		return PTR_ERR(hdmi->avdd_0v9);
++
++	hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8");
++	if (IS_ERR(hdmi->avdd_1v8))
++		return PTR_ERR(hdmi->avdd_1v8);
++
+ 	return 0;
+ }
+ 
+@@ -566,11 +577,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 		return ret;
+ 	}
+ 
++	ret = regulator_enable(hdmi->avdd_0v9);
++	if (ret) {
++		DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret);
++		goto err_avdd_0v9;
++	}
++
++	ret = regulator_enable(hdmi->avdd_1v8);
++	if (ret) {
++		DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret);
++		goto err_avdd_1v8;
++	}
++
+ 	ret = clk_prepare_enable(hdmi->ref_clk);
+ 	if (ret) {
+ 		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
+ 			      ret);
+-		return ret;
++		goto err_clk;
+ 	}
+ 
+ 	if (hdmi->chip_data == &rk3568_chip_data) {
+@@ -594,10 +617,19 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	 */
+ 	if (IS_ERR(hdmi->hdmi)) {
+ 		ret = PTR_ERR(hdmi->hdmi);
+-		drm_encoder_cleanup(encoder);
+-		clk_disable_unprepare(hdmi->ref_clk);
++		goto err_bind;
+ 	}
+ 
++	return 0;
++
++err_bind:
++	clk_disable_unprepare(hdmi->ref_clk);
++	drm_encoder_cleanup(encoder);
++err_clk:
++	regulator_disable(hdmi->avdd_1v8);
++err_avdd_1v8:
++	regulator_disable(hdmi->avdd_0v9);
++err_avdd_0v9:
+ 	return ret;
+ }
+ 
+@@ -608,6 +640,9 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
+ 
+ 	dw_hdmi_unbind(hdmi->hdmi);
+ 	clk_disable_unprepare(hdmi->ref_clk);
++
++	regulator_disable(hdmi->avdd_1v8);
++	regulator_disable(hdmi->avdd_0v9);
+ }
+ 
+ static const struct component_ops dw_hdmi_rockchip_ops = {

patch/kernel/archive/media-5.18/00-v11-10-24-dt-bindings-display-rockchip-dw-hdmi-Add-regulator-support.patch

@@ -0,0 +1,22 @@
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+index e6b8437a1e2d1..38ebb69830287 100644
+--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+@@ -28,6 +28,17 @@ properties:
+   reg-io-width:
+     const: 4
+ 
++  avdd-0v9-supply:
++    description:
++      A 0.9V supply that powers up the SoC internal circuitry. The actual pin name
++      varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes
++      HDMI_AVDD_1V0.
++
++  avdd-1v8-supply:
++    description:
++      A 1.8V supply that powers up the SoC internal circuitry. The pin name on the
++      SoC usually is HDMI_TX_AVDD_1V8.
++
+   clocks:
+     minItems: 2
+     items:

patch/kernel/archive/media-5.18/00-v11-11-24-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch

@@ -0,0 +1,154 @@
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index fe4f9556239ac..cb43e7b47157d 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -91,80 +91,88 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
+ 
+ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	{
+-		27000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++		30666000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40f3, 0x0000 },
+ 		},
+-	}, {
+-		36000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++	},  {
++		36800000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		40000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++	},  {
++		46000000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		54000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
++	},  {
++		61333000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		65000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
++	},  {
++		73600000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		66000000, {
+-			{ 0x013e, 0x0003},
+-			{ 0x217e, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		92000000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		74250000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		122666000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		83500000, {
+-			{ 0x0072, 0x0001},
++	},  {
++		147200000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		108000000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		184000000, {
++			{ 0x0051, 0x0002 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		106500000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		226666000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		146250000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		272000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
+-		148500000, {
+-			{ 0x0051, 0x0003},
+-			{ 0x214c, 0x0003},
+-			{ 0x4064, 0x0003}
++	},  {
++		340000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
++	},  {
++		600000000, {
++			{ 0x1a40, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
++		},
++	},  {
+ 		~0UL, {
+-			{ 0x00a0, 0x000a },
+-			{ 0x2001, 0x000f },
+-			{ 0x4002, 0x000f },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
+ 		},
+ 	}
+ };

patch/kernel/archive/media-5.18/00-v11-12-24-drm-rockchip-dw_hdmi-relax-mode_valid-hook.patch

@@ -0,0 +1,13 @@
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index cb43e7b47157d..a77a46a709809 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -259,7 +259,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
+ 	int i;
+ 
+ 	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
+-		if (pclk == mpll_cfg[i].mpixelclock) {
++		if (pclk <= mpll_cfg[i].mpixelclock) {
+ 			valid = true;
+ 			break;
+ 		}

patch/kernel/archive/media-5.18/00-v11-13-24-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch

@@ -0,0 +1,27 @@
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index a77a46a709809..ed480f6548f0e 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -180,20 +180,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+-		40000000,  { 0x0018, 0x0018, 0x0018 },
+-	}, {
+-		65000000,  { 0x0028, 0x0028, 0x0028 },
+-	}, {
+-		66000000,  { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		74250000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		83500000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		146250000, { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		148500000, { 0x0000, 0x0038, 0x0038 },
+-	}, {
++		600000000, { 0x0000, 0x0000, 0x0000 },
++	},  {
+ 		~0UL,      { 0x0000, 0x0000, 0x0000},
+ 	}
+ };

patch/kernel/archive/media-5.18/00-v11-14-24-drm-rockchip-dw_hdmi-add-default-594Mhz-clk-for-4K-60hz.patch

@@ -0,0 +1,12 @@
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index ed480f6548f0e..de8720fd7d5d6 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -191,6 +191,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
+ 	{ 74250000,  0x8009, 0x0004, 0x0272},
+ 	{ 148500000, 0x802b, 0x0004, 0x028d},
+ 	{ 297000000, 0x8039, 0x0005, 0x028d},
++	{ 594000000, 0x8039, 0x0000, 0x019d},
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+ 

patch/kernel/archive/media-5.18/00-v11-15-24-dt-bindings-display-rockchip-dw-hdmi-Make-unwedge-pinctrl-optional.patch

@@ -0,0 +1,12 @@
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+index 38ebb69830287..d7cb2b2be60e8 100644
+--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+@@ -89,6 +89,7 @@ properties:
+       The unwedge pinctrl entry shall drive the DDC SDA line low. This is
+       intended to work around a hardware errata that can cause the DDC I2C
+       bus to be wedged.
++    minItems: 1
+     items:
+       - const: default
+       - const: unwedge

patch/kernel/archive/media-5.18/00-v11-16-24-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch

@@ -0,0 +1,113 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+index 3839eef5e4f76..595fa2562cb8e 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+@@ -18,3 +18,7 @@ power-domain@RK3568_PD_PIPE {
+ 		#power-domain-cells = <0>;
+ 	};
+ };
++
++&vop {
++	compatible = "rockchip,rk3566-vop";
++};
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+index 5b0f528d68180..4deab90e83834 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -114,3 +114,7 @@ power-domain@RK3568_PD_PIPE {
+ 		#power-domain-cells = <0>;
+ 	};
+ };
++
++&vop {
++	compatible = "rockchip,rk3568-vop";
++};
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index 7cdef800cb3ce..fdb7a9a6ca743 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -129,6 +129,11 @@ opp-1800000000 {
+ 		};
+ 	};
+ 
++	display_subsystem: display-subsystem {
++		compatible = "rockchip,display-subsystem";
++		ports = <&vop_out>;
++	};
++
+ 	firmware {
+ 		scmi: scmi {
+ 			compatible = "arm,scmi-smc";
+@@ -569,6 +574,52 @@ gmac1_mtl_tx_setup: tx-queues-config {
+ 		};
+ 	};
+ 
++	vop: vop@fe040000 {
++		reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
++		reg-names = "regs", "gamma_lut";
++		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
++			 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
++		clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
++		iommus = <&vop_mmu>;
++		power-domains = <&power RK3568_PD_VO>;
++		rockchip,grf = <&grf>;
++		status = "disabled";
++
++		vop_out: ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			vp0: port@0 {
++				reg = <0>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++
++			vp1: port@1 {
++				reg = <1>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++
++			vp2: port@2 {
++				reg = <2>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++	};
++
++	vop_mmu: iommu@fe043e00 {
++		compatible = "rockchip,rk3568-iommu";
++		reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
++		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
++		clock-names = "aclk", "iface";
++		#iommu-cells = <0>;
++		status = "disabled";
++	};
++
+ 	qos_gpu: qos@fe128000 {
+ 		compatible = "rockchip,rk3568-qos", "syscon";
+ 		reg = <0x0 0xfe128000 0x0 0x20>;
+diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h
+new file mode 100644
+index 0000000000000..6e66a802b96a5
+--- /dev/null
++++ b/include/dt-bindings/soc/rockchip,vop2.h
+@@ -0,0 +1,14 @@
++/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
++
++#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
++#define __DT_BINDINGS_ROCKCHIP_VOP2_H
++
++#define ROCKCHIP_VOP2_EP_RGB0	1
++#define ROCKCHIP_VOP2_EP_HDMI0	2
++#define ROCKCHIP_VOP2_EP_EDP0	3
++#define ROCKCHIP_VOP2_EP_MIPI0	4
++#define ROCKCHIP_VOP2_EP_LVDS0	5
++#define ROCKCHIP_VOP2_EP_MIPI1	6
++#define ROCKCHIP_VOP2_EP_LVDS1	7
++
++#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */

patch/kernel/archive/media-5.18/00-v11-17-24-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch

@@ -0,0 +1,43 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index fdb7a9a6ca743..1a359bbf65300 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -620,6 +620,38 @@ vop_mmu: iommu@fe043e00 {
+ 		status = "disabled";
+ 	};
+ 
++	hdmi: hdmi@fe0a0000 {
++		compatible = "rockchip,rk3568-dw-hdmi";
++		reg = <0x0 0xfe0a0000 0x0 0x20000>;
++		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru PCLK_HDMI_HOST>,
++			 <&cru CLK_HDMI_SFR>,
++			 <&cru CLK_HDMI_CEC>,
++			 <&pmucru CLK_HDMI_REF>,
++			 <&cru HCLK_VO>;
++		clock-names = "iahb", "isfr", "cec", "ref";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
++		power-domains = <&power RK3568_PD_VO>;
++		reg-io-width = <4>;
++		rockchip,grf = <&grf>;
++		#sound-dai-cells = <0>;
++		status = "disabled";
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			hdmi_in: port@0 {
++				reg = <0>;
++			};
++
++			hdmi_out: port@1 {
++				reg = <1>;
++			};
++		};
++	};
++
+ 	qos_gpu: qos@fe128000 {
+ 		compatible = "rockchip,rk3568-qos", "syscon";
+ 		reg = <0x0 0xfe128000 0x0 0x20>;

patch/kernel/archive/media-5.18/00-v11-18-24-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch

@@ -0,0 +1,76 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+index a794a0ea5c701..096b66d7697e2 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3568.dtsi"
+ 
+ / {
+@@ -34,6 +35,17 @@ dc_12v: dc-12v {
+ 		regulator-max-microvolt = <12000000>;
+ 	};
+ 
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -189,6 +201,24 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -589,3 +619,20 @@ &usb2phy1_otg {
+ 	phy-supply = <&vcc5v0_usb_host>;
+ 	status = "okay";
+ };
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};

patch/kernel/archive/media-5.18/00-v11-19-24-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz64a.patch

@@ -0,0 +1,76 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+index dd7f4b9b686b8..6504f7ab3ea77 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -4,6 +4,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3566.dtsi"
+ 
+ / {
+@@ -35,6 +36,17 @@ fan: gpio_fan {
+ 		#cooling-cells = <2>;
+ 	};
+ 
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -248,6 +260,24 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	avdd-0v9-supply = <&vdda_0v9>;
++	avdd-1v8-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -685,3 +715,20 @@ &usb2phy1_otg {
+ 	phy-supply = <&vcc5v0_usb20_host>;
+ 	status = "okay";
+ };
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};

patch/kernel/archive/media-5.18/00-v11-21-24-drm-rockchip-Make-VOP-driver-optional.patch

@@ -0,0 +1,49 @@
+diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
+index fa5cfda4e90e3..22cf6c8402c89 100644
+--- a/drivers/gpu/drm/rockchip/Kconfig
++++ b/drivers/gpu/drm/rockchip/Kconfig
+@@ -23,8 +23,16 @@ config DRM_ROCKCHIP
+ 
+ if DRM_ROCKCHIP
+ 
++config ROCKCHIP_VOP
++	bool "Rockchip VOP driver"
++	default y
++	help
++	  This selects support for the VOP driver. You should enable it
++	  on older SoCs.
++
+ config ROCKCHIP_ANALOGIX_DP
+ 	bool "Rockchip specific extensions for Analogix DP driver"
++	depends on ROCKCHIP_VOP
+ 	help
+ 	  This selects support for Rockchip SoC specific extensions
+ 	  for the Analogix Core DP driver. If you want to enable DP
+diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
+index 1a56f696558ca..dfc5512fdb9f1 100644
+--- a/drivers/gpu/drm/rockchip/Makefile
++++ b/drivers/gpu/drm/rockchip/Makefile
+@@ -4,8 +4,9 @@
+ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
+ 
+ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
+-		rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o
++		rockchip_drm_gem.o
+ 
++rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
+ rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+index 0dc09d92d92d6..6ab0460819467 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+@@ -481,7 +481,7 @@ static int __init rockchip_drm_init(void)
+ 		return -ENODEV;
+ 
+ 	num_rockchip_sub_drivers = 0;
+-	ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP);
++	ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP);
+ 	ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
+ 				CONFIG_ROCKCHIP_LVDS);
+ 	ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,

patch/kernel/archive/media-5.18/00-v11-23-24-dt-bindings-display-rockchip-Add-binding-for-VOP2.patch

@@ -0,0 +1,146 @@
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
+new file mode 100644
+index 0000000000000..655d9b327f7d3
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
+@@ -0,0 +1,140 @@
++# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip SoC display controller (VOP2)
++
++description:
++  VOP2 (Video Output Processor v2) is the display controller for the Rockchip
++  series of SoCs which transfers the image data from a video memory
++  buffer to an external LCD interface.
++
++maintainers:
++  - Sandy Huang <hjc@rock-chips.com>
++  - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3566-vop
++      - rockchip,rk3568-vop
++
++  reg:
++    minItems: 1
++    items:
++      - description:
++          Must contain one entry corresponding to the base address and length
++          of the register space.
++      - description:
++          Can optionally contain a second entry corresponding to
++          the CRTC gamma LUT address.
++
++  interrupts:
++    maxItems: 1
++    description:
++      The VOP interrupt is shared by several interrupt sources, such as
++      frame start (VSYNC), line flag and other status interrupts.
++
++  clocks:
++    items:
++      - description: Clock for ddr buffer transfer.
++      - description: Clock for the ahb bus to R/W the phy regs.
++      - description: Pixel clock for video port 0.
++      - description: Pixel clock for video port 1.
++      - description: Pixel clock for video port 2.
++
++  clock-names:
++    items:
++      - const: aclk
++      - const: hclk
++      - const: dclk_vp0
++      - const: dclk_vp1
++      - const: dclk_vp2
++
++  rockchip,grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Phandle to GRF regs used for misc control
++
++  ports:
++    $ref: /schemas/graph.yaml#/properties/ports
++
++    properties:
++      port@0:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Output endpoint of VP0
++
++      port@1:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Output endpoint of VP1
++
++      port@2:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Output endpoint of VP2
++
++  iommus:
++    maxItems: 1
++
++  power-domains:
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - clocks
++  - clock-names
++  - ports
++
++additionalProperties: false
++
++examples:
++  - |
++        #include <dt-bindings/clock/rk3568-cru.h>
++        #include <dt-bindings/interrupt-controller/arm-gic.h>
++        #include <dt-bindings/power/rk3568-power.h>
++        bus {
++            #address-cells = <2>;
++            #size-cells = <2>;
++            vop: vop@fe040000 {
++                compatible = "rockchip,rk3568-vop";
++                reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
++                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++                clocks = <&cru ACLK_VOP>,
++                         <&cru HCLK_VOP>,
++                         <&cru DCLK_VOP0>,
++                         <&cru DCLK_VOP1>,
++                         <&cru DCLK_VOP2>;
++                clock-names = "aclk",
++                              "hclk",
++                              "dclk_vp0",
++                              "dclk_vp1",
++                              "dclk_vp2";
++                power-domains = <&power RK3568_PD_VO>;
++                iommus = <&vop_mmu>;
++                vop_out: ports {
++                    #address-cells = <1>;
++                    #size-cells = <0>;
++                    vp0: port@0 {
++                        reg = <0>;
++                        #address-cells = <1>;
++                        #size-cells = <0>;
++                    };
++                    vp1: port@1 {
++                        reg = <1>;
++                        #address-cells = <1>;
++                        #size-cells = <0>;
++                    };
++                    vp2: port@2 {
++                        reg = <2>;
++                        #address-cells = <1>;
++                        #size-cells = <0>;
++                    };
++                };
++            };
++        };

patch/kernel/archive/media-5.18/00-v11-24-24-dt-bindings-display-rockchip-dw-hdmi-fix-ports-description.patch

@@ -0,0 +1,41 @@
+diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+index d7cb2b2be60e8..7e59dee15a5f4 100644
+--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+@@ -97,27 +97,21 @@ properties:
+   ports:
+     $ref: /schemas/graph.yaml#/properties/ports
+ 
+-    properties:
+-      port:
+-        $ref: /schemas/graph.yaml#/$defs/port-base
+-        unevaluatedProperties: false
++    patternProperties:
++      "^port(@0)?$":
++        $ref: /schemas/graph.yaml#/properties/port
+         description: Input of the DWC HDMI TX
+-
+         properties:
++          endpoint:
++            description: Connection to the VOP
+           endpoint@0:
+-            $ref: /schemas/graph.yaml#/properties/endpoint
+             description: Connection to the VOPB
+-
+           endpoint@1:
+-            $ref: /schemas/graph.yaml#/properties/endpoint
+             description: Connection to the VOPL
+-
+-        required:
+-          - endpoint@0
+-          - endpoint@1
+-
+-    required:
+-      - port
++    properties:
++      port@1:
++        $ref: /schemas/graph.yaml#/properties/port
++        description: Output of the DWC HDMI TX
+ 
+   rockchip,grf:
+     $ref: /schemas/types.yaml#/definitions/phandle

patch/kernel/archive/media-5.18/01-v5-1-5-dt-bindings-soc-grf-add-rk3566-pipe-grf-compatible.patch

@@ -0,0 +1,12 @@
+diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+index b2ba7bed89b2..3be3cfd52f7b 100644
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -15,6 +15,7 @@ properties:
+       - items:
+           - enum:
+               - rockchip,rk3288-sgrf
++              - rockchip,rk3566-pipe-grf
+               - rockchip,rk3568-usb2phy-grf
+               - rockchip,rv1108-usbgrf
+           - const: syscon

patch/kernel/archive/media-5.18/01-v5-2-5-soc-rockchip-set-dwc3-clock-for-rk3566.patch

@@ -0,0 +1,35 @@
+diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
+index 494cf2b5bf7b..384461b70684 100644
+--- a/drivers/soc/rockchip/grf.c
++++ b/drivers/soc/rockchip/grf.c
+@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk3399_grf __initconst = {
+ 	.num_values = ARRAY_SIZE(rk3399_defaults),
+ };
+ 
++#define RK3566_GRF_USB3OTG0_CON1	0x0104
++
++static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
++	{ "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
++	{ "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
++	{ "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
++};
++
++static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
++	.values = rk3566_defaults,
++	.num_values = ARRAY_SIZE(rk3566_defaults),
++};
++
++
+ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
+ 	{
+ 		.compatible = "rockchip,rk3036-grf",
+@@ -130,6 +144,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
+ 	}, {
+ 		.compatible = "rockchip,rk3399-grf",
+ 		.data = (void *)&rk3399_grf,
++	}, {
++		.compatible = "rockchip,rk3566-pipe-grf",
++		.data = (void *)&rk3566_pipegrf,
+ 	},
+ 	{ /* sentinel */ },
+ };

patch/kernel/archive/media-5.18/01-v5-3-5-arm64-dts-rockchip-add-rk356x-dwc3-usb3-nodes.patch

@@ -0,0 +1,103 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+index 3839eef5e4f7..0b957068ff89 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+@@ -6,6 +6,10 @@ / {
+ 	compatible = "rockchip,rk3566";
+ };
+ 
++&pipegrf {
++	compatible = "rockchip,rk3566-pipe-grf", "syscon";
++};
++
+ &power {
+ 	power-domain@RK3568_PD_PIPE {
+ 		reg = <RK3568_PD_PIPE>;
+@@ -18,3 +22,10 @@ power-domain@RK3568_PD_PIPE {
+ 		#power-domain-cells = <0>;
+ 	};
+ };
++
++&usb_host0_xhci {
++	phys = <&usb2phy0_otg>;
++	phy-names = "usb2-phy";
++	extcon = <&usb2phy0>;
++	maximum-speed = "high-speed";
++};
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+index 5b0f528d6818..8ba9334f9753 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -99,6 +99,10 @@ opp-1992000000 {
+ 	};
+ };
+ 
++&pipegrf {
++	compatible = "rockchip,rk3568-pipe-grf", "syscon";
++};
++
+ &power {
+ 	power-domain@RK3568_PD_PIPE {
+ 		reg = <RK3568_PD_PIPE>;
+@@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE {
+ 		#power-domain-cells = <0>;
+ 	};
+ };
++
++&usb_host0_xhci {
++	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
++	phy-names = "usb2-phy", "usb3-phy";
++};
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index 7cdef800cb3c..ca20d7b91fe5 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -230,6 +230,40 @@ scmi_shmem: sram@0 {
+ 		};
+ 	};
+ 
++	usb_host0_xhci: usb@fcc00000 {
++		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
++		reg = <0x0 0xfcc00000 0x0 0x400000>;
++		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
++			 <&cru ACLK_USB3OTG0>;
++		clock-names = "ref_clk", "suspend_clk",
++			      "bus_clk";
++		dr_mode = "host";
++		phy_type = "utmi_wide";
++		power-domains = <&power RK3568_PD_PIPE>;
++		resets = <&cru SRST_USB3OTG0>;
++		snps,dis_u2_susphy_quirk;
++		status = "disabled";
++	};
++
++	usb_host1_xhci: usb@fd000000 {
++		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
++		reg = <0x0 0xfd000000 0x0 0x400000>;
++		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
++			 <&cru ACLK_USB3OTG1>;
++		clock-names = "ref_clk", "suspend_clk",
++			      "bus_clk";
++		dr_mode = "host";
++		phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
++		phy-names = "usb2-phy", "usb3-phy";
++		phy_type = "utmi_wide";
++		power-domains = <&power RK3568_PD_PIPE>;
++		resets = <&cru SRST_USB3OTG1>;
++		snps,dis_u2_susphy_quirk;
++		status = "disabled";
++	};
++
+ 	gic: interrupt-controller@fd400000 {
+ 		compatible = "arm,gic-v3";
+ 		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
+@@ -297,7 +331,6 @@ pmu_io_domains: io-domains {
+ 	};
+ 
+ 	pipegrf: syscon@fdc50000 {
+-		compatible = "rockchip,rk3568-pipe-grf", "syscon";
+ 		reg = <0x0 0xfdc50000 0x0 0x1000>;
+ 	};
+ 

patch/kernel/archive/media-5.18/01-v5-4-5-arm64-dts-rockchip-enable-dwc3-on-quartz64-a.patch

@@ -0,0 +1,62 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+index dd7f4b9b686b..141a433429b5 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -151,6 +151,16 @@ vcc5v0_usb20_host: vcc5v0_usb20_host {
+ 		vin-supply = <&vcc5v0_usb>;
+ 	};
+ 
++	vcc5v0_usb20_otg: vcc5v0_usb20_otg {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vcc5v0_usb20_otg";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dcdc_boost>;
++	};
++
+ 	vcc3v3_sd: vcc3v3_sd {
+ 		compatible = "regulator-fixed";
+ 		enable-active-low;
+@@ -187,6 +197,10 @@ vcc_wl: vcc_wl {
+ 	};
+ };
+ 
++&combphy1 {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&vdd_cpu>;
+ };
+@@ -672,6 +686,29 @@ &usb_host1_ohci {
+ 	status = "okay";
+ };
+ 
++&usb_host0_xhci {
++	status = "okay";
++};
++
++/* usb3 controller is muxed with sata1 */
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb20_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vcc5v0_usb20_otg>;
++	status = "okay";
++};
++
+ &usb2phy1 {
+ 	status = "okay";
+ };

patch/kernel/archive/media-5.18/01-v5-5-5-arm64-dts-rockchip-add-usb3-support-to-rk3568-evb1-v10.patch

@@ -0,0 +1,85 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+index a794a0ea5c70..622be8be9813 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+@@ -103,6 +103,18 @@ vcc5v0_usb_host: vcc5v0-usb-host {
+ 		vin-supply = <&vcc5v0_usb>;
+ 	};
+ 
++	vcc5v0_usb_otg: vcc5v0-usb-otg {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_otg_en>;
++		regulator-name = "vcc5v0_usb_otg";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++
+ 	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc3v3_lcd0_n";
+@@ -136,6 +148,14 @@ regulator-state-mem {
+ 	};
+ };
+ 
++&combphy0 {
++	status = "okay";
++};
++
++&combphy1 {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&vdd_cpu>;
+ };
+@@ -507,6 +527,9 @@ usb {
+ 		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+ 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
+ 	};
+ };
+ 
+@@ -568,6 +591,11 @@ &usb_host0_ohci {
+ 	status = "okay";
+ };
+ 
++&usb_host0_xhci {
++	extcon = <&usb2phy0>;
++	status = "okay";
++};
++
+ &usb_host1_ehci {
+ 	status = "okay";
+ };
+@@ -576,6 +604,24 @@ &usb_host1_ohci {
+ 	status = "okay";
+ };
+ 
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	vbus-supply = <&vcc5v0_usb_otg>;
++	status = "okay";
++};
++
+ &usb2phy1 {
+ 	status = "okay";
+ };

patch/kernel/archive/media-5.18/05-v91-i2s-mclk.patch

@@ -0,0 +1,84 @@
+diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
+index 606ae6cd918b..ee8924ac0093 100644
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -13,6 +13,8 @@
+ #include <dt-bindings/clock/rk3568-cru.h>
+ #include "clk.h"
+ 
++#define RK3568_GRF_SOC_CON1	0x504
++#define RK3568_GRF_SOC_CON2	0x508
+ #define RK3568_GRF_SOC_STATUS0	0x580
+ 
+ enum rk3568_pmu_plls {
+@@ -247,13 +249,13 @@ PNAME(dpll_gpll_cpll_p)			= { "dpll", "gpll", "cpll" };
+ PNAME(clk_ddr1x_p)			= { "clk_ddrphy1x_src", "dpll" };
+ PNAME(gpll200_gpll150_gpll100_xin24m_p)	= { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
+ PNAME(gpll100_gpll75_gpll50_p)		= { "gpll_100m", "gpll_75m", "cpll_50m" };
+-PNAME(i2s0_mclkout_tx_p)		= { "clk_i2s0_8ch_tx", "xin_osc0_half" };
+-PNAME(i2s0_mclkout_rx_p)		= { "clk_i2s0_8ch_rx", "xin_osc0_half" };
+-PNAME(i2s1_mclkout_tx_p)		= { "clk_i2s1_8ch_tx", "xin_osc0_half" };
+-PNAME(i2s1_mclkout_rx_p)		= { "clk_i2s1_8ch_rx", "xin_osc0_half" };
+-PNAME(i2s2_mclkout_p)			= { "clk_i2s2_2ch", "xin_osc0_half" };
+-PNAME(i2s3_mclkout_tx_p)		= { "clk_i2s3_2ch_tx", "xin_osc0_half" };
+-PNAME(i2s3_mclkout_rx_p)		= { "clk_i2s3_2ch_rx", "xin_osc0_half" };
++PNAME(i2s0_mclkout_tx_p)		= { "mclk_i2s0_8ch_tx", "xin_osc0_half" };
++PNAME(i2s0_mclkout_rx_p)		= { "mclk_i2s0_8ch_rx", "xin_osc0_half" };
++PNAME(i2s1_mclkout_tx_p)		= { "mclk_i2s1_8ch_tx", "xin_osc0_half" };
++PNAME(i2s1_mclkout_rx_p)		= { "mclk_i2s1_8ch_rx", "xin_osc0_half" };
++PNAME(i2s2_mclkout_p)			= { "mclk_i2s2_2ch", "xin_osc0_half" };
++PNAME(i2s3_mclkout_tx_p)		= { "mclk_i2s3_2ch_tx", "xin_osc0_half" };
++PNAME(i2s3_mclkout_rx_p)		= { "mclk_i2s3_2ch_rx", "xin_osc0_half" };
+ PNAME(mclk_pdm_p)			= { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
+ PNAME(clk_i2c_p)			= { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
+ PNAME(gpll200_gpll150_gpll100_p)	= { "gpll_200m", "gpll_150m", "gpll_100m" };
+@@ -307,6 +309,12 @@ PNAME(clk_mac_2top_p)			= { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
+ PNAME(clk_pwm0_p)			= { "xin24m", "clk_pdpmu" };
+ PNAME(aclk_rkvdec_pre_p)		= { "gpll", "cpll" };
+ PNAME(clk_rkvdec_core_p)		= { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
++PNAME(i2s1_mclkout_p)			= { "i2s1_mclkout_rx", "i2s1_mclkout_tx" };
++PNAME(i2s3_mclkout_p)			= { "i2s3_mclkout_rx", "i2s3_mclkout_tx" };
++PNAME(i2s1_mclk_rx_ioe_p)		= { "i2s1_mclkin_rx", "i2s1_mclkout_rx" };
++PNAME(i2s1_mclk_tx_ioe_p)		= { "i2s1_mclkin_tx", "i2s1_mclkout_tx" };
++PNAME(i2s2_mclk_ioe_p)			= { "i2s2_mclkin", "i2s2_mclkout" };
++PNAME(i2s3_mclk_ioe_p)			= { "i2s3_mclkin", "i2s3_mclkout" };
+ 
+ static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
+ 	[ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll",  mux_pll_p,
+@@ -704,6 +712,19 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
+ 			RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
+ 			RK3568_CLKGATE_CON(7), 11, GFLAGS),
+ 
++	MUXGRF(I2S1_MCLKOUT, "i2s1_mclkout", i2s1_mclkout_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			RK3568_GRF_SOC_CON1, 5, 1, MFLAGS),
++	MUXGRF(I2S3_MCLKOUT, "i2s3_mclkout", i2s3_mclkout_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			RK3568_GRF_SOC_CON2, 15, 1, MFLAGS),
++	MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p,  0,
++			RK3568_GRF_SOC_CON2, 0, 1, MFLAGS),
++	MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p,  0,
++			RK3568_GRF_SOC_CON2, 1, 1, MFLAGS),
++	MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p,  0,
++			RK3568_GRF_SOC_CON2, 2, 1, MFLAGS),
++	MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p,  0,
++			RK3568_GRF_SOC_CON2, 3, 1, MFLAGS),
++
+ 	GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
+ 			RK3568_CLKGATE_CON(5), 14, GFLAGS),
+ 	COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
+diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
+index d29890865150..251445cf7632 100644
+--- a/include/dt-bindings/clock/rk3568-cru.h
++++ b/include/dt-bindings/clock/rk3568-cru.h
+@@ -479,6 +479,12 @@
+ #define CPLL_25M		416
+ #define CPLL_100M		417
+ #define SCLK_DDRCLK		418
++#define I2S1_MCLKOUT		419
++#define I2S3_MCLKOUT		420
++#define I2S1_MCLK_RX_IOE	421
++#define I2S1_MCLK_TX_IOE	422
++#define I2S2_MCLK_IOE		423
++#define I2S3_MCLK_IOE		424
+ 
+ #define PCLK_CORE_PVTM		450
+ 

patch/kernel/archive/media-5.18/05-v91-irq-gic-v3-its.patch

@@ -0,0 +1,192 @@
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -45,6 +45,7 @@
+ 
+ #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
+ #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
++#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE	(1 << 2)
+ 
+ #define RD_LOCAL_LPI_ENABLED                    BIT(0)
+ #define RD_LOCAL_PENDTABLE_PREALLOCATED         BIT(1)
+@@ -2176,6 +2177,11 @@
+ {
+ 	struct page *prop_page;
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		pr_err("ITS ALLOCATE PROP WORKAROUND\n");
++		gfp_flags |= GFP_DMA;
++	}
++
+ 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
+ 	if (!prop_page)
+ 		return NULL;
+@@ -2299,6 +2305,7 @@
+ 	u32 alloc_pages, psz;
+ 	struct page *page;
+ 	void *base;
++	gfp_t gfp_flags;
+ 
+ 	psz = baser->psz;
+ 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
+@@ -2310,7 +2317,10 @@
+ 		order = get_order(GITS_BASER_PAGES_MAX * psz);
+ 	}
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
++	gfp_flags = GFP_KERNEL | __GFP_ZERO;
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		gfp_flags |= GFP_DMA;
++	page = alloc_pages_node(its->numa_node, gfp_flags, order);
+ 	if (!page)
+ 		return -ENOMEM;
+ 
+@@ -2356,6 +2366,13 @@
+ 
+ 	its_write_baser(its, baser, val);
+ 	tmp = baser->val;
++
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		if (tmp & GITS_BASER_SHAREABILITY_MASK)
++			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
++		else
++			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
++	}
+ 
+ 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
+ 		/*
+@@ -2939,6 +2956,10 @@
+ {
+ 	struct page *pend_page;
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		gfp_flags |= GFP_DMA;
++	}
++
+ 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
+ 				get_order(LPI_PENDBASE_SZ));
+ 	if (!pend_page)
+@@ -3083,6 +3104,9 @@
+ 
+ 	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
+ 	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
++
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+ 
+ 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+@@ -3108,6 +3132,9 @@
+ 	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
+ 	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
++
+ 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+ 		/*
+ 		 * The HW reports non-shareable, we must remove the
+@@ -3271,7 +3298,12 @@
+ 
+ 	/* Allocate memory for 2nd level table */
+ 	if (!table[idx]) {
+-		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
++		if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++			gfp_flags |= GFP_DMA;
++		}
++
++		page = alloc_pages_node(its->numa_node, gfp_flags,
+ 					get_order(baser->psz));
+ 		if (!page)
+ 			return false;
+@@ -3360,6 +3392,7 @@
+ 	int nr_lpis;
+ 	int nr_ites;
+ 	int sz;
++	gfp_t gfp_flags;
+ 
+ 	if (!its_alloc_device_table(its, dev_id))
+ 		return NULL;
+@@ -3367,7 +3400,11 @@
+ 	if (WARN_ON(!is_power_of_2(nvecs)))
+ 		nvecs = roundup_pow_of_two(nvecs);
+ 
+-	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++	gfp_flags = GFP_KERNEL;
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		gfp_flags |= GFP_DMA;
++
++	dev = kzalloc(sizeof(*dev), gfp_flags);
+ 	/*
+ 	 * Even if the device wants a single LPI, the ITT must be
+ 	 * sized as a power of two (and you need at least one bit...).
+@@ -3375,7 +3412,8 @@
+ 	nr_ites = max(2, nvecs);
+ 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
+ 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
+-	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
++
++	itt = kzalloc_node(sz, gfp_flags, its->numa_node);
+ 	if (alloc_lpis) {
+ 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
+ 		if (lpi_map)
+@@ -4695,6 +4733,13 @@
+ 	 * page. Trick it into doing the right thing...
+ 	 */
+ 	its->vlpi_redist_offset = SZ_128K;
++	return true;
++}
++
++static bool __maybe_unused its_enable_quirk_rk3568(void *data)
++{
++	gic_rdists->flags |= RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
++
+ 	return true;
+ }
+ 
+@@ -4745,6 +4790,13 @@
+ 	},
+ #endif
+ 	{
++		.desc	= "ITS: Rockchip RK3568 force no_local_cache",
++		.iidr	= 0x0201743b,
++		.mask	= 0xffffffff,
++		.init	= its_enable_quirk_rk3568,
++	},
++
++	{
+ 	}
+ };
+ 
+@@ -4999,6 +5051,7 @@
+ 	struct page *page;
+ 	u32 ctlr;
+ 	int err;
++	gfp_t gfp_flags;
+ 
+ 	its_base = its_map_one(res, &err);
+ 	if (!its_base)
+@@ -5052,7 +5105,11 @@
+ 
+ 	its->numa_node = numa_node;
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++	gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA;
++//	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++//		gfp_flags |= GFP_DMA;
++
++	page = alloc_pages_node(its->numa_node, gfp_flags,
+ 				get_order(ITS_CMD_QUEUE_SZ));
+ 	if (!page) {
+ 		err = -ENOMEM;
+@@ -5082,6 +5139,9 @@
+ 
+ 	gits_write_cbaser(baser, its->base + GITS_CBASER);
+ 	tmp = gits_read_cbaser(its->base + GITS_CBASER);
++
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+ 
+ 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
+