fix SPIDEV overlay and add SPI-JEDEC-NOR overlay
This commit is contained in:
Martin Ayotte
parent
9b10c1c1f3
commit
fadde96f2b
@ -12,11 +12,12 @@ diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts
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index e69de29..576e190 100644
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
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@@ -0,0 +1,20 @@
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@@ -0,0 +1,21 @@
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+# SPDX-License-Identifier: GPL-2.0
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+dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
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+ rockchip-i2c7.dtbo \
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+ rockchip-i2c8.dtbo \
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+ rockchip-spi-jedec-nor.dtbo \
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+ rockchip-spi-spidev.dtbo \
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+ rockchip-uart4.dtbo \
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+ rockchip-w1-gpio.dtbo
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@ -37,7 +38,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arc
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index e69de29..9512445 100644
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
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@@ -0,0 +1,76 @@
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@@ -0,0 +1,101 @@
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+This document describes overlays provided in the kernel packages
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+For generic Armbian overlays documentation please see
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+https://docs.armbian.com/User-Guide_Allwinner_overlays/
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@ -64,6 +65,29 @@ index e69de29..9512445 100644
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+
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+I2C8 pins (SCL, SDA): GPIO1-C5, GPIO1-C4
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+
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+### spi-jedec-nor
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+
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+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
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+supported by the kernel SPI NOR driver
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+
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+SPI 0 pins (MOSI, MISO, SCK, CS): GPIO3_A5, GPIO3_A4, GPIO3_A6, GPIO3_A7
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+SPI 1 pins (MOSI, MISO, SCK, CS): GPIO1_A7, GPIO1_B0, GPIO1_B1, GPIO1_B2
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+SPI 2 pins (MOSI, MISO, SCK, CS): GPIO1_C0, GPIO1_B7, GPIO1_C1, GPIO1_C2
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+SPI 3 pins (MOSI, MISO, SCK, CS): GPIO2_B2, GPIO2_B1, GPIO2_B3, GPIO2_B4
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+
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+Parameters:
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+
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+param_spinor_spi_bus (int)
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+ SPI bus to activate SPI NOR flash support on
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+ Required
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+ Supported values: 0, 1, 2
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+
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+param_spinor_max_freq (int)
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+ Maximum SPI frequency
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+ Optional
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+ Default: 1000000
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+ Range: 3000 - 100000000
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+
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+### spi-spidev
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+
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+Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
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@ -71,6 +95,8 @@ index e69de29..9512445 100644
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+
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+SPI 0 pins (MOSI, MISO, SCK, CS): GPIO3_A5, GPIO3_A4, GPIO3_A6, GPIO3_A7
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+SPI 1 pins (MOSI, MISO, SCK, CS): GPIO1_A7, GPIO1_B0, GPIO1_B1, GPIO1_B2
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+SPI 2 pins (MOSI, MISO, SCK, CS): GPIO1_C0, GPIO1_B7, GPIO1_C1, GPIO1_C2
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+SPI 3 pins (MOSI, MISO, SCK, CS): GPIO2_B2, GPIO2_B1, GPIO2_B3, GPIO2_B4
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+
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+Parameters:
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+
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@ -119,7 +145,7 @@ new file mode 100644
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index 0000000..d4c39e2
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-fixup.scr-cmd
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@@ -0,0 +1,44 @@
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@@ -0,0 +1,62 @@
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+# overlays fixup script
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+# implements (or rather substitutes) overlay arguments functionality
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+# using u-boot scripting, environment variables and "fdt" command
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@ -135,9 +161,27 @@ index 0000000..d4c39e2
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+setexpr tmp_pin ${tmp_bank} + ${tmp_pin}'
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+
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+
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+if test -n "${param_spinor_spi_bus}"; then
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+ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@ff1c0000"
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+ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@ff1d0000"
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+ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@ff1e0000"
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+ test "${param_spinor_spi_bus}" = "3" && setenv tmp_spi_path "spi@ff1f0000"
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+ fdt set /${tmp_spi_path} status "okay"
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+ fdt set /${tmp_spi_path}/spiflash@0 status "okay"
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+ if test -n "${param_spinor_max_freq}"; then
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+ fdt set /${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
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+ fi
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+ if test "${param_spinor_spi_cs}" = "1"; then
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+ fdt set /${tmp_spi_path}/spiflash@0 reg "<1>"
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+ fi
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+ env delete tmp_spi_path
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+fi
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+
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+if test -n "${param_spidev_spi_bus}"; then
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+ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@ff1c0000"
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+ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@ff1d0000"
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+ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@ff1e0000"
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+ test "${param_spidev_spi_bus}" = "3" && setenv tmp_spi_path "spi@ff1f0000"
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+ fdt set /${tmp_spi_path} status "okay"
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+ fdt set /${tmp_spi_path}/spidev status "okay"
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+ if test -n "${param_spidev_max_freq}"; then
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@ -198,12 +242,12 @@ index 0000000..54bc844
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+ };
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+ };
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+};
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diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts
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diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-jedec-nor.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-jedec-nor.dts
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new file mode 100644
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index 0000000..fe8fb14
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index 0000000..3a2be38
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts
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@@ -0,0 +1,42 @@
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+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-jedec-nor.dts
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@@ -0,0 +1,72 @@
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+/dts-v1/;
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+/plugin/;
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+
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@ -213,8 +257,88 @@ index 0000000..fe8fb14
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ spi0 = "/soc/spi@ff1c0000";
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+ spi1 = "/soc/spi@ff1d0000";
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+ spi0 = "/spi@ff1c0000";
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+ spi1 = "/spi@ff1d0000";
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+ spi2 = "/spi@ff1e0000";
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+ spi3 = "/spi@ff1f0000";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&spi0>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spiflash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ fragment@2 {
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+ target = <&spi1>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spiflash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ fragment@3 {
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+ target = <&spi2>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spiflash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ fragment@4 {
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+ target = <&spi3>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spiflash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+};
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diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts
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new file mode 100644
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index 0000000..fe8fb14
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts
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@@ -0,0 +1,72 @@
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "rockchip,rk3399";
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+
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+ fragment@0 {
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+ target-path = "/aliases";
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+ __overlay__ {
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+ spi0 = "/spi@ff1c0000";
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+ spi1 = "/spi@ff1d0000";
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+ spi2 = "/spi@ff1e0000";
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+ spi3 = "/spi@ff1f0000";
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+ };
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+ };
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+
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@ -245,6 +369,34 @@ index 0000000..fe8fb14
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+ };
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+ };
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+ };
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+
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+ fragment@3 {
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+ target = <&spi2>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spidev {
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+ compatible = "spidev";
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+ status = "disabled";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ };
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+ };
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+ };
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+
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+ fragment@4 {
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+ target = <&spi3>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spidev {
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+ compatible = "spidev";
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+ status = "disabled";
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+ reg = <0>;
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+ spi-max-frequency = <1000000>;
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+ };
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+ };
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+ };
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+};
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diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-uart4.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-uart4.dts
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new file mode 100644
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