From fadde96f2b0a0221b9e7abe7efe7f94377f3e651 Mon Sep 17 00:00:00 2001 From: Martin Ayotte Date: Wed, 24 Jul 2019 17:41:52 -0400 Subject: [PATCH] fix SPIDEV overlay and add SPI-JEDEC-NOR overlay --- .../general-rockchip-overlays.patch | 170 +++++++++++++++++- 1 file changed, 161 insertions(+), 9 deletions(-) diff --git a/patch/kernel/rockchip64-dev/general-rockchip-overlays.patch b/patch/kernel/rockchip64-dev/general-rockchip-overlays.patch index c6a23d29fb..ae7eaf5a51 100644 --- a/patch/kernel/rockchip64-dev/general-rockchip-overlays.patch +++ b/patch/kernel/rockchip64-dev/general-rockchip-overlays.patch @@ -12,11 +12,12 @@ diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts index e69de29..576e190 100644 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile -@@ -0,0 +1,20 @@ +@@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0 +dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + rockchip-i2c7.dtbo \ + rockchip-i2c8.dtbo \ ++ rockchip-spi-jedec-nor.dtbo \ + rockchip-spi-spidev.dtbo \ + rockchip-uart4.dtbo \ + rockchip-w1-gpio.dtbo @@ -37,7 +38,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arc index e69de29..9512445 100644 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays -@@ -0,0 +1,76 @@ +@@ -0,0 +1,101 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Allwinner_overlays/ @@ -64,6 +65,29 @@ index e69de29..9512445 100644 + +I2C8 pins (SCL, SDA): GPIO1-C5, GPIO1-C4 + ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): GPIO3_A5, GPIO3_A4, GPIO3_A6, GPIO3_A7 ++SPI 1 pins (MOSI, MISO, SCK, CS): GPIO1_A7, GPIO1_B0, GPIO1_B1, GPIO1_B2 ++SPI 2 pins (MOSI, MISO, SCK, CS): GPIO1_C0, GPIO1_B7, GPIO1_C1, GPIO1_C2 ++SPI 3 pins (MOSI, MISO, SCK, CS): GPIO2_B2, GPIO2_B1, GPIO2_B3, GPIO2_B4 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ +### spi-spidev + +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, @@ -71,6 +95,8 @@ index e69de29..9512445 100644 + +SPI 0 pins (MOSI, MISO, SCK, CS): GPIO3_A5, GPIO3_A4, GPIO3_A6, GPIO3_A7 +SPI 1 pins (MOSI, MISO, SCK, CS): GPIO1_A7, GPIO1_B0, GPIO1_B1, GPIO1_B2 ++SPI 2 pins (MOSI, MISO, SCK, CS): GPIO1_C0, GPIO1_B7, GPIO1_C1, GPIO1_C2 ++SPI 3 pins (MOSI, MISO, SCK, CS): GPIO2_B2, GPIO2_B1, GPIO2_B3, GPIO2_B4 + +Parameters: + @@ -119,7 +145,7 @@ new file mode 100644 index 0000000..d4c39e2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-fixup.scr-cmd -@@ -0,0 +1,44 @@ +@@ -0,0 +1,62 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command @@ -135,9 +161,27 @@ index 0000000..d4c39e2 +setexpr tmp_pin ${tmp_bank} + ${tmp_pin}' + + ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@ff1c0000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@ff1d0000" ++ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@ff1e0000" ++ test "${param_spinor_spi_bus}" = "3" && setenv tmp_spi_path "spi@ff1f0000" ++ fdt set /${tmp_spi_path} status "okay" ++ fdt set /${tmp_spi_path}/spiflash@0 status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /${tmp_spi_path}/spiflash@0 reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ +if test -n "${param_spidev_spi_bus}"; then + test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@ff1c0000" + test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@ff1d0000" ++ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@ff1e0000" ++ test "${param_spidev_spi_bus}" = "3" && setenv tmp_spi_path "spi@ff1f0000" + fdt set /${tmp_spi_path} status "okay" + fdt set /${tmp_spi_path}/spidev status "okay" + if test -n "${param_spidev_max_freq}"; then @@ -198,12 +242,12 @@ index 0000000..54bc844 + }; + }; +}; -diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts +diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-jedec-nor.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-jedec-nor.dts new file mode 100644 -index 0000000..fe8fb14 +index 0000000..3a2be38 --- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts -@@ -0,0 +1,42 @@ ++++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-jedec-nor.dts +@@ -0,0 +1,72 @@ +/dts-v1/; +/plugin/; + @@ -213,8 +257,88 @@ index 0000000..fe8fb14 + fragment@0 { + target-path = "/aliases"; + __overlay__ { -+ spi0 = "/soc/spi@ff1c0000"; -+ spi1 = "/soc/spi@ff1d0000"; ++ spi0 = "/spi@ff1c0000"; ++ spi1 = "/spi@ff1d0000"; ++ spi2 = "/spi@ff1e0000"; ++ spi3 = "/spi@ff1f0000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&spi3>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts +new file mode 100644 +index 0000000..fe8fb14 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-spi-spidev.dts +@@ -0,0 +1,72 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "rockchip,rk3399"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/spi@ff1c0000"; ++ spi1 = "/spi@ff1d0000"; ++ spi2 = "/spi@ff1e0000"; ++ spi3 = "/spi@ff1f0000"; + }; + }; + @@ -245,6 +369,34 @@ index 0000000..fe8fb14 + }; + }; + }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&spi3>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-uart4.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-uart4.dts new file mode 100644