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H3 NanoPi Neo Air: updated wifi patch

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updated patch enabling wifi for 4.17 changing model identifier, wifi powerup sequence, and wifi module control
This commit is contained in:
Karabek 2018-06-03 15:56:29 +02:00 committed by GitHub
parent cfc87b876b
commit d51cce6ceb
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 0 additions and 86 deletions
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86
patch/kernel/sunxi-dev/unresolved/wifi-nanopi-neo-air.patch
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@ -1,86 +0,0 @@
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
old mode 100644
new mode 100755
index 03ff6f8..ddbb92b
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
@@ -47,7 +47,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "FriendlyARM NanoPi NEO Air";
+ model = "FriendlyElec NanoPi NEO Air";
compatible = "friendlyarm,nanopi-neo-air", "allwinner,sun8i-h3";
aliases {
@@ -58,6 +58,13 @@
stdout-path = "serial0:115200n8";
};
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_en_neoair>;
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ };
+
leds {
compatible = "gpio-leds";
@@ -86,6 +86,13 @@
};
};
+&r_pio {
+ wifi_en_neoair: wifi_en_pin@0 {
+ allwinner,pins = "PL7";
+ allwinner,function = "gpio_out";
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
@@ -84,6 +99,42 @@
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ drive-strength = <40>;
+ /* eMMC is missing pull-ups */
+ bias-pull-up;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;