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clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

Browse Source 
https://groups.google.com/forum/#!topic/linux-sunxi/kztLGFTBgZw
This commit is contained in:
Igor Pecovnik 2017-05-03 14:11:17 +02:00
parent d1b8144bd6
commit c9b2303427
1 changed files with 15 additions and 0 deletions
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15
patch/kernel/sunxi-next/a31-hdmi-out-fix.patch Normal file
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@ -0,0 +1,15 @@
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
old mode 100644
new mode 100755
index 8ca07fe..0cca360
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -556,7 +556,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
0x12c, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
- 0x12c, 0, 4, 24, 3, BIT(31),
+ 0x130, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",