From c9b23034274e0531aafe4bd527a4290fa8481a23 Mon Sep 17 00:00:00 2001 From: Igor Pecovnik Date: Wed, 3 May 2017 14:11:17 +0200 Subject: [PATCH] clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset https://groups.google.com/forum/#!topic/linux-sunxi/kztLGFTBgZw --- patch/kernel/sunxi-next/a31-hdmi-out-fix.patch | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 patch/kernel/sunxi-next/a31-hdmi-out-fix.patch diff --git a/patch/kernel/sunxi-next/a31-hdmi-out-fix.patch b/patch/kernel/sunxi-next/a31-hdmi-out-fix.patch new file mode 100644 index 0000000000..e3404cce11 --- /dev/null +++ b/patch/kernel/sunxi-next/a31-hdmi-out-fix.patch @@ -0,0 +1,15 @@ +diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +old mode 100644 +new mode 100755 +index 8ca07fe..0cca360 +--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c ++++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +@@ -556,7 +556,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents, + 0x12c, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); + static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents, +- 0x12c, 0, 4, 24, 3, BIT(31), ++ 0x130, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); + + static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",