mixtile-blade3: mainline: updates to mainline DT with "working" RTL8169's
- For 6.18 + 6.19
- mixtile-blade3: add 4-pin header fan at 40c
- mixtile-blade3: add gpu nodes
- mixtile-blade3: add vcc5v0-host-en "usb" pinctrl
- somehow results in 2 working RTL8169's behind the ASM1182e on pcie2x1l0
- which just means the _schematics lie_
- mixtile-blade3: drop rst pinctrl from pcie2x1l0 and pcie2x1l1
- this is me probably being stupid, but also required for working ASM1182e/RTL8169
- Status of this mainline port:
- Initially started by Joshua Riek (2023?)
- I then added some PCIe3x4 stuff, but never got around to finishing it
- Specifically, the 2 FUSB302's are beyond me for now
- One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom.
- See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect.
- A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch
- Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered
- Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working!
- All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now.
- Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff.
- Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf
- Those clearly lie.
This commit is contained in:
Ricardo Pardini
Igor
parent
df970b8bee
commit
9c4f8fa339
@ -1,5 +1,20 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// rpardini, early 2026:
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// - Status of this mainline port:
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// - Initially started by Joshua Riek (2023?)
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// - I then added some PCIe3x4 stuff, but never got around to finishing it
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// - Specifically, the 2 FUSB302's are beyond me for now
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// - One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom.
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// - See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect.
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// - A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch
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// - Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered
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// - Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working!
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// - All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now.
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// - Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff.
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// - Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf
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// - Those clearly lie.
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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@ -20,6 +35,18 @@
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stdout-path = "serial2:1500000n8";
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};
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fan: pwm-fan {
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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cooling-levels = <0 50 100 150 200 255>;
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pwms = <&pwm8 0 250000 0>; /* aka GPIO3_D0 / PWM8_M2 On 4-pin fan header */
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fan-supply = <&vcc5v0_sys>;
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pulses-per-revolution = <2>;
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interrupt-parent = <&gpio3>; /* GPIO GPIO3_B1/PWM2_M1 */
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interrupts = <RK_PB1 IRQ_TYPE_EDGE_FALLING>; // On 4-pin fan header
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status = "okay";
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};
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vcc12v_dcin: vcc12v-dcin-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc12v_dcin";
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@ -186,6 +213,11 @@
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mem-supply = <&vdd_cpu_lit_mem_s0>;
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};
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&gpu {
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mali-supply = <&vdd_gpu_s0>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0m2_xfer>;
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@ -270,17 +302,40 @@
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status = "okay";
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};
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&pcie2x1l0 {
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/* Temperature sensor near the center of the SoC */
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&package_thermal {
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polling-delay = <1000>;
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trips {
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package_hot: package_hot {
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hysteresis = <2000>;
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temperature = <40000>; /* 40 celsius */
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type = "active";
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};
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};
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cooling-maps {
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map0 {
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cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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trip = <&package_hot>;
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};
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};
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};
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&pcie2x1l0 { // combphy1, to ASM1182e
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reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_0_rst>;
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rockchip,init-delay-ms = <100>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&pcie2_0_rst>;
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status = "okay";
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};
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&pcie2x1l1 {
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&pcie2x1l1 { // combphy2, to miniPCIe socket
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reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_1_rst>;
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rockchip,init-delay-ms = <100>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&pcie2_1_rst>;
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status = "okay";
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};
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@ -296,6 +351,10 @@
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status = "okay";
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};
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&pd_gpu {
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domain-supply = <&vdd_gpu_s0>;
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};
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&pinctrl {
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sdmmc {
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sdmmc_pwr: sdmmc-pwr {
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@ -303,15 +362,15 @@
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};
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};
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pcie2 {
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pcie2_0_rst: pcie2-0-rst {
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rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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//pcie2 {
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// pcie2_0_rst: pcie2-0-rst {
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// rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
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// };
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pcie2_1_rst: pcie2-1-rst {
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rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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// pcie2_1_rst: pcie2-1-rst {
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// rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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// };
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//};
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pcie3 {
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pcie3_rst: pcie3-rst {
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@ -320,12 +379,22 @@
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pcie3_vcc3v3_en: pcie3-vcc3v3-en {
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rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
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// drives a ETA5050V33S2F regulator for 3.3v to VCC3V3_PI6C
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};
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};
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usb {
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vcc5v0_host_en: vcc5v0-host-en {
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rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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// Schematics say this drives a ETA6027S2F current limiter enabling VBUS5V0_TYPEC0.
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// But it _must_ somehow power the PCIe switch too, as both RTL8169's come up working with this!
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};
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};
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// GPIO3_C6: 3 RK_PC6 is for power to the minipci 2.0 slot
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};
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&pwm8 {
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pinctrl-names = "active";
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&pwm8 { // 4-pin FAN HEADER, PWM OUTPUT
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pinctrl-0 = <&pwm8m2_pins>;
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status = "okay";
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};
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@ -1,5 +1,20 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// rpardini, early 2026:
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// - Status of this mainline port:
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// - Initially started by Joshua Riek (2023?)
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// - I then added some PCIe3x4 stuff, but never got around to finishing it
|
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// - Specifically, the 2 FUSB302's are beyond me for now
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||||
// - One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom.
|
||||
// - See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect.
|
||||
// - A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch
|
||||
// - Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered
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// - Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working!
|
||||
// - All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now.
|
||||
// - Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff.
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// - Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf
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// - Those clearly lie.
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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@ -20,6 +35,18 @@
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stdout-path = "serial2:1500000n8";
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};
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fan: pwm-fan {
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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cooling-levels = <0 50 100 150 200 255>;
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pwms = <&pwm8 0 250000 0>; /* aka GPIO3_D0 / PWM8_M2 On 4-pin fan header */
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fan-supply = <&vcc5v0_sys>;
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pulses-per-revolution = <2>;
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interrupt-parent = <&gpio3>; /* GPIO GPIO3_B1/PWM2_M1 */
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interrupts = <RK_PB1 IRQ_TYPE_EDGE_FALLING>; // On 4-pin fan header
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status = "okay";
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};
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vcc12v_dcin: vcc12v-dcin-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc12v_dcin";
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@ -186,6 +213,11 @@
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mem-supply = <&vdd_cpu_lit_mem_s0>;
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};
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&gpu {
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mali-supply = <&vdd_gpu_s0>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0m2_xfer>;
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@ -270,17 +302,40 @@
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status = "okay";
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};
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&pcie2x1l0 {
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/* Temperature sensor near the center of the SoC */
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&package_thermal {
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polling-delay = <1000>;
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trips {
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package_hot: package_hot {
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hysteresis = <2000>;
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temperature = <40000>; /* 40 celsius */
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type = "active";
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};
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};
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cooling-maps {
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map0 {
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cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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trip = <&package_hot>;
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};
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};
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};
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&pcie2x1l0 { // combphy1, to ASM1182e
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reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_0_rst>;
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rockchip,init-delay-ms = <100>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&pcie2_0_rst>;
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status = "okay";
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};
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&pcie2x1l1 {
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&pcie2x1l1 { // combphy2, to miniPCIe socket
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reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_1_rst>;
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rockchip,init-delay-ms = <100>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&pcie2_1_rst>;
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status = "okay";
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};
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@ -296,6 +351,10 @@
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status = "okay";
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};
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&pd_gpu {
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domain-supply = <&vdd_gpu_s0>;
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};
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&pinctrl {
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sdmmc {
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sdmmc_pwr: sdmmc-pwr {
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@ -303,15 +362,15 @@
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};
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};
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pcie2 {
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pcie2_0_rst: pcie2-0-rst {
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rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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//pcie2 {
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// pcie2_0_rst: pcie2-0-rst {
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// rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
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// };
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pcie2_1_rst: pcie2-1-rst {
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rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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// pcie2_1_rst: pcie2-1-rst {
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// rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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// };
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//};
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pcie3 {
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pcie3_rst: pcie3-rst {
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@ -320,12 +379,22 @@
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pcie3_vcc3v3_en: pcie3-vcc3v3-en {
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rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
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// drives a ETA5050V33S2F regulator for 3.3v to VCC3V3_PI6C
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};
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};
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usb {
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vcc5v0_host_en: vcc5v0-host-en {
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rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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// Schematics say this drives a ETA6027S2F current limiter enabling VBUS5V0_TYPEC0.
|
||||
// But it _must_ somehow power the PCIe switch too, as both RTL8169's come up working with this!
|
||||
};
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};
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// GPIO3_C6: 3 RK_PC6 is for power to the minipci 2.0 slot
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};
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&pwm8 {
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pinctrl-names = "active";
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&pwm8 { // 4-pin FAN HEADER, PWM OUTPUT
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pinctrl-0 = <&pwm8m2_pins>;
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status = "okay";
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};
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