From 9c4f8fa339161f9618ba8cdb06d67b32a2cb4da2 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Sun, 31 Aug 2025 19:22:09 +0200 Subject: [PATCH] mixtile-blade3: mainline: updates to mainline DT with "working" RTL8169's - For 6.18 + 6.19 - mixtile-blade3: add 4-pin header fan at 40c - mixtile-blade3: add gpu nodes - mixtile-blade3: add vcc5v0-host-en "usb" pinctrl - somehow results in 2 working RTL8169's behind the ASM1182e on pcie2x1l0 - which just means the _schematics lie_ - mixtile-blade3: drop rst pinctrl from pcie2x1l0 and pcie2x1l1 - this is me probably being stupid, but also required for working ASM1182e/RTL8169 - Status of this mainline port: - Initially started by Joshua Riek (2023?) - I then added some PCIe3x4 stuff, but never got around to finishing it - Specifically, the 2 FUSB302's are beyond me for now - One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom. - See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect. - A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch - Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered - Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working! - All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now. - Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff. - Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf - Those clearly lie. --- .../dt/rk3588-mixtile-blade3.dts | 101 +++++++++++++++--- .../dt/rk3588-mixtile-blade3.dts | 101 +++++++++++++++--- 2 files changed, 170 insertions(+), 32 deletions(-) diff --git a/patch/kernel/archive/rockchip64-6.18/dt/rk3588-mixtile-blade3.dts b/patch/kernel/archive/rockchip64-6.18/dt/rk3588-mixtile-blade3.dts index ef0adae48e..399eef9cb0 100644 --- a/patch/kernel/archive/rockchip64-6.18/dt/rk3588-mixtile-blade3.dts +++ b/patch/kernel/archive/rockchip64-6.18/dt/rk3588-mixtile-blade3.dts @@ -1,5 +1,20 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// rpardini, early 2026: +// - Status of this mainline port: +// - Initially started by Joshua Riek (2023?) +// - I then added some PCIe3x4 stuff, but never got around to finishing it +// - Specifically, the 2 FUSB302's are beyond me for now +// - One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom. +// - See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect. +// - A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch +// - Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered +// - Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working! +// - All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now. +// - Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff. +// - Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf +// - Those clearly lie. + /dts-v1/; #include @@ -20,6 +35,18 @@ stdout-path = "serial2:1500000n8"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 50 100 150 200 255>; + pwms = <&pwm8 0 250000 0>; /* aka GPIO3_D0 / PWM8_M2 On 4-pin fan header */ + fan-supply = <&vcc5v0_sys>; + pulses-per-revolution = <2>; + interrupt-parent = <&gpio3>; /* GPIO GPIO3_B1/PWM2_M1 */ + interrupts = ; // On 4-pin fan header + status = "okay"; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -186,6 +213,11 @@ mem-supply = <&vdd_cpu_lit_mem_s0>; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -270,17 +302,40 @@ status = "okay"; }; -&pcie2x1l0 { +/* Temperature sensor near the center of the SoC */ +&package_thermal { + polling-delay = <1000>; + + trips { + package_hot: package_hot { + hysteresis = <2000>; + temperature = <40000>; /* 40 celsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&package_hot>; + }; + }; +}; + + +&pcie2x1l0 { // combphy1, to ASM1182e reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + rockchip,init-delay-ms = <100>; + //pinctrl-names = "default"; + //pinctrl-0 = <&pcie2_0_rst>; status = "okay"; }; -&pcie2x1l1 { +&pcie2x1l1 { // combphy2, to miniPCIe socket reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>; + rockchip,init-delay-ms = <100>; + //pinctrl-names = "default"; + //pinctrl-0 = <&pcie2_1_rst>; status = "okay"; }; @@ -296,6 +351,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { sdmmc { sdmmc_pwr: sdmmc-pwr { @@ -303,15 +362,15 @@ }; }; - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; + //pcie2 { + // pcie2_0_rst: pcie2-0-rst { + // rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + // }; - pcie2_1_rst: pcie2-1-rst { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; + // pcie2_1_rst: pcie2-1-rst { + // rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + // }; + //}; pcie3 { pcie3_rst: pcie3-rst { @@ -320,12 +379,22 @@ pcie3_vcc3v3_en: pcie3-vcc3v3-en { rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + // drives a ETA5050V33S2F regulator for 3.3v to VCC3V3_PI6C }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + // Schematics say this drives a ETA6027S2F current limiter enabling VBUS5V0_TYPEC0. + // But it _must_ somehow power the PCIe switch too, as both RTL8169's come up working with this! + }; + }; + + // GPIO3_C6: 3 RK_PC6 is for power to the minipci 2.0 slot }; -&pwm8 { - pinctrl-names = "active"; +&pwm8 { // 4-pin FAN HEADER, PWM OUTPUT pinctrl-0 = <&pwm8m2_pins>; status = "okay"; }; diff --git a/patch/kernel/archive/rockchip64-6.19/dt/rk3588-mixtile-blade3.dts b/patch/kernel/archive/rockchip64-6.19/dt/rk3588-mixtile-blade3.dts index ef0adae48e..399eef9cb0 100644 --- a/patch/kernel/archive/rockchip64-6.19/dt/rk3588-mixtile-blade3.dts +++ b/patch/kernel/archive/rockchip64-6.19/dt/rk3588-mixtile-blade3.dts @@ -1,5 +1,20 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// rpardini, early 2026: +// - Status of this mainline port: +// - Initially started by Joshua Riek (2023?) +// - I then added some PCIe3x4 stuff, but never got around to finishing it +// - Specifically, the 2 FUSB302's are beyond me for now +// - One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom. +// - See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect. +// - A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch +// - Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered +// - Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working! +// - All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now. +// - Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff. +// - Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf +// - Those clearly lie. + /dts-v1/; #include @@ -20,6 +35,18 @@ stdout-path = "serial2:1500000n8"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 50 100 150 200 255>; + pwms = <&pwm8 0 250000 0>; /* aka GPIO3_D0 / PWM8_M2 On 4-pin fan header */ + fan-supply = <&vcc5v0_sys>; + pulses-per-revolution = <2>; + interrupt-parent = <&gpio3>; /* GPIO GPIO3_B1/PWM2_M1 */ + interrupts = ; // On 4-pin fan header + status = "okay"; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -186,6 +213,11 @@ mem-supply = <&vdd_cpu_lit_mem_s0>; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -270,17 +302,40 @@ status = "okay"; }; -&pcie2x1l0 { +/* Temperature sensor near the center of the SoC */ +&package_thermal { + polling-delay = <1000>; + + trips { + package_hot: package_hot { + hysteresis = <2000>; + temperature = <40000>; /* 40 celsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&package_hot>; + }; + }; +}; + + +&pcie2x1l0 { // combphy1, to ASM1182e reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + rockchip,init-delay-ms = <100>; + //pinctrl-names = "default"; + //pinctrl-0 = <&pcie2_0_rst>; status = "okay"; }; -&pcie2x1l1 { +&pcie2x1l1 { // combphy2, to miniPCIe socket reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>; + rockchip,init-delay-ms = <100>; + //pinctrl-names = "default"; + //pinctrl-0 = <&pcie2_1_rst>; status = "okay"; }; @@ -296,6 +351,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { sdmmc { sdmmc_pwr: sdmmc-pwr { @@ -303,15 +362,15 @@ }; }; - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; + //pcie2 { + // pcie2_0_rst: pcie2-0-rst { + // rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + // }; - pcie2_1_rst: pcie2-1-rst { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; + // pcie2_1_rst: pcie2-1-rst { + // rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + // }; + //}; pcie3 { pcie3_rst: pcie3-rst { @@ -320,12 +379,22 @@ pcie3_vcc3v3_en: pcie3-vcc3v3-en { rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + // drives a ETA5050V33S2F regulator for 3.3v to VCC3V3_PI6C }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + // Schematics say this drives a ETA6027S2F current limiter enabling VBUS5V0_TYPEC0. + // But it _must_ somehow power the PCIe switch too, as both RTL8169's come up working with this! + }; + }; + + // GPIO3_C6: 3 RK_PC6 is for power to the minipci 2.0 slot }; -&pwm8 { - pinctrl-names = "active"; +&pwm8 { // 4-pin FAN HEADER, PWM OUTPUT pinctrl-0 = <&pwm8m2_pins>; status = "okay"; };