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Add NanoPi R2C support (#3138)

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* Add NanoPi R2C support
* Bring NanoPi R2C, R2S to edge
This commit is contained in:
Ruikai (Rick) Liu 2021-09-16 04:20:35 +08:00 committed by GitHub
parent 0069ad60a6
commit 687c363918
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
11 changed files with 2499 additions and 4 deletions
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11
config/boards/nanopi-r2c.conf Normal file
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@ -0,0 +1,11 @@
# Rockchip RK3328 quad core 1GB 2 x GBE USB2
BOARD_NAME="Nanopi R2C"
BOARDFAMILY="rockchip64"
BOOTCONFIG="nanopi-r2s-rk3328_defconfig"
KERNEL_TARGET="current,edge"
DEFAULT_CONSOLE="serial"
MODULES="g_serial"
MODULES_BLACKLIST="rockchipdrm analogix_dp dw_mipi_dsi dw_hdmi gpu_sched lima hantro_vpu"
SERIALCON="ttyS2:1500000,ttyGS0"
BUILD_DESKTOP="no"
BOOT_FDT_FILE="rockchip/rk3328-nanopi-r2-rev06.dtb"

1
config/kernel/linux-rockchip64-current.config
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@ -2908,6 +2908,7 @@ CONFIG_NATIONAL_PHY=m
# CONFIG_NXP_TJA11XX_PHY is not set
CONFIG_AT803X_PHY=m
CONFIG_QSEMI_PHY=m
CONFIG_MOTORCOMM_PHY=y
CONFIG_REALTEK_PHY=m
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y

4
config/sources/families/include/rockchip64_common.inc
View File

@ -38,7 +38,7 @@ else # rk3308, rk3328
fi
if [[ $BOARD == nanopi-r2s || $BOARD == nanopineo3 || $BOARD == orangepi-r1plus || $BOARD == renegade || $BOARD == rockpi-e || $BOARD == station-m1 || $BOARD == z28pro ]]; then
if [[ $BOARD == nanopi-r2s || $BOARD == nanopi-r2c || $BOARD == nanopineo3 || $BOARD == orangepi-r1plus || $BOARD == renegade || $BOARD == rockpi-e || $BOARD == station-m1 || $BOARD == z28pro ]]; then
BOOT_USE_BLOBS=yes
BOOT_SOC=rk3328
@ -345,7 +345,7 @@ family_tweaks()
chroot $SDCARD /bin/bash -c "systemctl --no-reload enable z28pro-bluetooth.service >/dev/null 2>&1"
elif [[ $BOARD == nanopi-r2s || $BOARD == orangepi-r1plus ]]; then
elif [[ $BOARD == nanopi-r2s || $BOARD == nanopi-r2c || $BOARD == orangepi-r1plus ]]; then
# rename USB based network to lan0
mkdir -p $SDCARD/etc/udev/rules.d/

5
config/targets.conf
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@ -336,6 +336,11 @@ nanopi-r2s current bullseye cli s
nanopi-r2s current focal cli stable yes
nanopi-r2s edge hirsute cli stable yes
# nanopi-r2c
nanopi-r2c current focal minimal stable yes
nanopi-r2c current buster cli stable yes
nanopi-r2c current bullseye cli stable yes
nanopi-r2c current focal cli stable yes
# nanopi-r4s
nanopi-r4s current focal minimal stable yes

95
patch/kernel/archive/rockchip64-5.10/add-board-nanopi-r2c.patch Normal file
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@ -0,0 +1,95 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts
new file mode 100644
index 000000000000..6322f59939b8
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2-rev00.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R2C";
+ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
+};
+
+&mach {
+ hwrev = <6>;
+ model = "NanoPi R2C";
+};
+
+&rgmiim1_pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <1 RK_PB4 2 &pcfg_pull_none_8ma>,
+ /* mac_rxclk */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 RK_PD1 2 &pcfg_pull_none_8ma>,
+ /* mac_clk */
+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 RK_PB2 2 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <1 RK_PB3 2 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <1 RK_PB0 2 &pcfg_pull_none_8ma>,
+ /* mac_txd0 */
+ <1 RK_PB1 2 &pcfg_pull_none_8ma>,
+ /* mac_rxd3 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <1 RK_PC0 2 &pcfg_pull_none_8ma>,
+ /* mac_txd2 */
+ <1 RK_PC1 2 &pcfg_pull_none_8ma>,
+
+ /* mac_txclk */
+ <0 RK_PB0 1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 RK_PD0 1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 RK_PC0 1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 RK_PC7 1 &pcfg_pull_none>,
+ /* mac_txd2 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+};
+
+/delete-node/ &rtl8211e;
+
+&gmac2io {
+ phy-handle = <&ethphy3>;
+ snps,reset-delays-us = <0 15000 50000>;
+ tx_delay = <0x22>;
+ rx_delay = <0x12>;
+ mdio {
+
+ ethphy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+ //reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ keep-clkout-on;
+ };
+ };
+};

3
patch/kernel/archive/rockchip64-5.10/add-boards-to-dts-makefile.patch
View File

@ -2,10 +2,11 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi
index 26661c7b7..1462ed38b 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,4 +1,18 @@
@@ -1,4 +1,19 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev00.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev06.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev20.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3-rev02.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb

467
patch/kernel/archive/rockchip64-5.10/net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch Normal file
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@ -0,0 +1,467 @@
From 5d6862cc5eac1679d7a4ef388f7c9bbc70e76770 Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Mon, 5 Jul 2021 17:03:00 +0800
Subject: [PATCH] net: phy: Add driver for Motorcomm YT85xx PHYs
Signed-off-by: hmz007 <hmz007@gmail.com>
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/motorcomm.c | 346 ++++++++++++++++++++++++++++++++++
include/linux/motorcomm_phy.h | 68 +++++++
4 files changed, 420 insertions(+)
create mode 100644 drivers/net/phy/motorcomm.c
create mode 100644 include/linux/motorcomm_phy.h
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..626ec44248dc 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -223,6 +223,11 @@ config MICROSEMI_PHY
help
Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
+config MOTORCOMM_PHY
+ tristate "Motorcomm PHYs"
+ help
+ Supports the YT8010, YT8510, YT8511, YT8512 PHYs.
+
config NATIONAL_PHY
tristate "National Semiconductor PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..c99b00bc24b5 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o
obj-$(CONFIG_MICROSEMI_PHY) += mscc/
+obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
new file mode 100644
index 000000000000..c53b5b88b226
--- /dev/null
+++ b/drivers/net/phy/motorcomm.c
@@ -0,0 +1,345 @@
+/*
+ * drivers/net/phy/motorcomm.c
+ *
+ * Driver for Motorcomm PHYs
+ *
+ * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
+ *
+ * Copyright (c) 2019 Motorcomm, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Support : Motorcomm Phys:
+ * Giga phys: yt8511, yt8521
+ * 100/10 Phys : yt8512, yt8512b, yt8510
+ * Automotive 100Mb Phys : yt8010
+ * Automotive 100/10 hyper range Phys: yt8510
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/motorcomm_phy.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+
+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
+{
+ int ret;
+ int val;
+
+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+ if (ret < 0)
+ return ret;
+
+ val = phy_read(phydev, REG_DEBUG_DATA);
+
+ return val;
+}
+
+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
+{
+ int ret;
+
+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write(phydev, REG_DEBUG_DATA, val);
+
+ return ret;
+}
+
+static int yt8010_config_aneg(struct phy_device *phydev)
+{
+ phydev->speed = SPEED_100;
+ return 0;
+}
+
+static int yt8512_clk_init(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
+ if (val < 0)
+ return val;
+
+ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
+
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
+ if (ret < 0)
+ return ret;
+
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
+ if (val < 0)
+ return val;
+
+ val |= YT8512_CONTROL1_RMII_EN;
+
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
+ if (ret < 0)
+ return ret;
+
+ val = phy_read(phydev, MII_BMCR);
+ if (val < 0)
+ return val;
+
+ val |= YT_SOFTWARE_RESET;
+ ret = phy_write(phydev, MII_BMCR, val);
+
+ return ret;
+}
+
+static int yt8512_led_init(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+ int mask;
+
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
+ if (val < 0)
+ return val;
+
+ val |= YT8512_LED0_ACT_BLK_IND;
+
+ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
+ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
+ YT8512_LED0_BT_ON_EN;
+ val &= ~mask;
+
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
+ if (ret < 0)
+ return ret;
+
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
+ if (val < 0)
+ return val;
+
+ val |= YT8512_LED1_BT_ON_EN;
+
+ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
+ val &= ~mask;
+
+ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
+
+ return ret;
+}
+
+static int yt8512_config_init(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+
+ ret = yt8512_clk_init(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = yt8512_led_init(phydev);
+
+ /* disable auto sleep */
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
+ if (val < 0)
+ return val;
+
+ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
+
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
+static int yt8512_read_status(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+ int speed, speed_mode, duplex;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+ if (val < 0)
+ return val;
+
+ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
+ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
+ switch (speed_mode) {
+ case 0:
+ speed = SPEED_10;
+ break;
+ case 1:
+ speed = SPEED_100;
+ break;
+ case 2:
+ case 3:
+ default:
+ speed = SPEED_UNKNOWN;
+ break;
+ }
+
+ phydev->speed = speed;
+ phydev->duplex = duplex;
+
+ return 0;
+}
+
+static int yt8521_config_init(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+
+ /* disable auto sleep */
+ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
+ if (val < 0)
+ return val;
+
+ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
+ if (ret < 0)
+ return ret;
+
+ /* switch to access UTP */
+ ret = ytphy_write_ext(phydev, 0xa000, 0);
+ if (ret < 0)
+ return ret;
+
+ /* enable RXC clock when no wire plug */
+ val = ytphy_read_ext(phydev, 0xc);
+ if (val < 0)
+ return val;
+
+ val &= ~(1 << 12);
+ ret = ytphy_write_ext(phydev, 0xc, val);
+ if (ret < 0)
+ return ret;
+
+ /* output SyncE clock (125mhz) even link is down */
+ ret = ytphy_write_ext(phydev, 0xa012, 0x38);
+ if (ret < 0)
+ return ret;
+
+ /* disable rgmii clk 2ns delay */
+ val = ytphy_read_ext(phydev, 0xa001);
+ if (val < 0)
+ return val;
+
+ val &= ~(1 << 8);
+ ret = ytphy_write_ext(phydev, 0xa001, val);
+ if (ret < 0)
+ return ret;
+
+ /* setup delay */
+ val = (1 << 10) | (0xf << 4) | 5;
+ ret = ytphy_write_ext(phydev, 0xa003, val);
+ if (ret < 0)
+ return ret;
+
+ /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
+ ytphy_write_ext(phydev, 0xa00b, 0xe004);
+ ytphy_write_ext(phydev, 0xa00c, 0);
+ ytphy_write_ext(phydev, 0xa00d, 0x2600);
+ ytphy_write_ext(phydev, 0xa00e, 0x0070);
+ ytphy_write_ext(phydev, 0xa00f, 0x000a);
+
+ return 0;
+}
+
+static int yt8521_config_intr(struct phy_device *phydev)
+{
+ int val;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+ val = BIT(14) | BIT(13) | BIT(11) | BIT(10);
+ else
+ val = 0;
+
+ return phy_write(phydev, REG_INT_MASK, val);
+}
+
+static int yt8521_ack_interrupt(struct phy_device *phydev)
+{
+ int val;
+
+ val = phy_read(phydev, REG_INT_STATUS);
+ phydev_dbg(phydev, "intr status 0x04%x\n", val);
+
+ return (val < 0) ? val : 0;
+}
+
+static struct phy_driver ytphy_drvs[] = {
+ {
+ .phy_id = PHY_ID_YT8010,
+ .name = "YT8010 Automotive Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .config_aneg = yt8010_config_aneg,
+ .read_status = genphy_read_status,
+ }, {
+ .phy_id = PHY_ID_YT8510,
+ .name = "YT8510 100/10Mb Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .read_status = genphy_read_status,
+ }, {
+ .phy_id = PHY_ID_YT8511,
+ .name = "YT8511 Gigabit Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_GBIT_FEATURES,
+ .read_status = genphy_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ }, {
+ .phy_id = PHY_ID_YT8512,
+ .name = "YT8512 Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .config_init = yt8512_config_init,
+ .read_status = yt8512_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ }, {
+ .phy_id = PHY_ID_YT8512B,
+ .name = "YT8512B Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .config_init = yt8512_config_init,
+ .read_status = yt8512_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ }, {
+ .phy_id = PHY_ID_YT8521,
+ .name = "YT8521 Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ /* PHY_GBIT_FEATURES */
+ .config_init = yt8521_config_init,
+ .ack_interrupt = yt8521_ack_interrupt,
+ .config_intr = yt8521_config_intr,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ },
+};
+
+module_phy_driver(ytphy_drvs);
+
+MODULE_DESCRIPTION("Motorcomm PHY driver");
+MODULE_AUTHOR("Leilei Zhao");
+MODULE_LICENSE("GPL");
+
+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
+ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h
new file mode 100644
index 000000000000..1e48c3671b69
--- /dev/null
+++ b/include/linux/motorcomm_phy.h
@@ -0,0 +1,67 @@
+/*
+ * include/linux/motorcomm_phy.h
+ *
+ * Motorcomm PHY IDs
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef _MOTORCOMM_PHY_H
+#define _MOTORCOMM_PHY_H
+
+#define MOTORCOMM_PHY_ID_MASK 0x00000fff
+
+#define PHY_ID_YT8010 0x00000309
+#define PHY_ID_YT8510 0x00000109
+#define PHY_ID_YT8511 0x0000010a
+#define PHY_ID_YT8512 0x00000118
+#define PHY_ID_YT8512B 0x00000128
+#define PHY_ID_YT8521 0x0000011a
+
+#define REG_PHY_SPEC_STATUS 0x11
+#define REG_INT_MASK 0x12
+#define REG_INT_STATUS 0x13
+#define REG_DEBUG_ADDR_OFFSET 0x1e
+#define REG_DEBUG_DATA 0x1f
+
+#define YT8512_EXTREG_AFE_PLL 0x50
+#define YT8512_EXTREG_EXTEND_COMBO 0x4000
+#define YT8512_EXTREG_LED0 0x40c0
+#define YT8512_EXTREG_LED1 0x40c3
+
+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
+
+#define YT_SOFTWARE_RESET 0x8000
+
+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
+#define YT8512_CONTROL1_RMII_EN 0x0001
+#define YT8512_LED0_ACT_BLK_IND 0x1000
+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
+#define YT8512_LED0_BT_BLK_EN 0x0002
+#define YT8512_LED0_HT_BLK_EN 0x0004
+#define YT8512_LED0_COL_BLK_EN 0x0008
+#define YT8512_LED0_BT_ON_EN 0x0010
+#define YT8512_LED1_BT_ON_EN 0x0010
+#define YT8512_LED1_TXACT_BLK_EN 0x0100
+#define YT8512_LED1_RXACT_BLK_EN 0x0200
+#define YT8512_SPEED_MODE 0xc000
+#define YT8512_DUPLEX 0x2000
+
+#define YT8512_SPEED_MODE_BIT 14
+#define YT8512_DUPLEX_BIT 13
+#define YT8512_EN_SLEEP_SW_BIT 15
+
+#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
+#define YT8521_EN_SLEEP_SW_BIT 15
+
+#define YT8521_SPEED_MODE 0xc000
+#define YT8521_DUPLEX 0x2000
+#define YT8521_SPEED_MODE_BIT 14
+#define YT8521_DUPLEX_BIT 13
+#define YT8521_LINK_STATUS_BIT 10
+
+#endif /* _MOTORCOMM_PHY_H */

95
patch/kernel/archive/rockchip64-5.14/add-board-nanopi-r2c.patch Normal file
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@ -0,0 +1,95 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts
new file mode 100644
index 000000000000..6322f59939b8
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2-rev00.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R2C";
+ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
+};
+
+&mach {
+ hwrev = <6>;
+ model = "NanoPi R2C";
+};
+
+&rgmiim1_pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <1 RK_PB4 2 &pcfg_pull_none_8ma>,
+ /* mac_rxclk */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 RK_PD1 2 &pcfg_pull_none_8ma>,
+ /* mac_clk */
+ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 RK_PB2 2 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <1 RK_PB3 2 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <1 RK_PB0 2 &pcfg_pull_none_8ma>,
+ /* mac_txd0 */
+ <1 RK_PB1 2 &pcfg_pull_none_8ma>,
+ /* mac_rxd3 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <1 RK_PC0 2 &pcfg_pull_none_8ma>,
+ /* mac_txd2 */
+ <1 RK_PC1 2 &pcfg_pull_none_8ma>,
+
+ /* mac_txclk */
+ <0 RK_PB0 1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 RK_PB4 1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 RK_PD0 1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 RK_PC0 1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 RK_PC1 1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 RK_PC7 1 &pcfg_pull_none>,
+ /* mac_txd2 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+};
+
+/delete-node/ &rtl8211e;
+
+&gmac2io {
+ phy-handle = <&ethphy3>;
+ snps,reset-delays-us = <0 15000 50000>;
+ tx_delay = <0x22>;
+ rx_delay = <0x12>;
+ mdio {
+
+ ethphy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+ //reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ keep-clkout-on;
+ };
+ };
+};

1360
patch/kernel/archive/rockchip64-5.14/add-board-nanopi-r2s.patch Normal file
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File diff suppressed because it is too large Load Diff

5
patch/kernel/archive/rockchip64-5.14/add-boards-to-dts-makefile.patch
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@ -2,11 +2,14 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi
index 26661c7b7..1462ed38b 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,4 +1,15 @@
@@ -1,4 +1,18 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev00.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev06.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev20.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-z28pro.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb

457
patch/kernel/archive/rockchip64-5.14/net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch Normal file
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@ -0,0 +1,457 @@
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 698bea312adc..626ec44248dc 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -223,6 +223,11 @@ config MICROSEMI_PHY
help
Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
+config MOTORCOMM_PHY
+ tristate "Motorcomm PHYs"
+ help
+ Supports the YT8010, YT8510, YT8511, YT8512 PHYs.
+
config NATIONAL_PHY
tristate "National Semiconductor PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a13e402074cf..c99b00bc24b5 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o
obj-$(CONFIG_MICROSEMI_PHY) += mscc/
+obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
new file mode 100644
index 000000000000..c53b5b88b226
--- /dev/null
+++ b/drivers/net/phy/motorcomm.c
@@ -0,0 +1,350 @@
+/*
+ * drivers/net/phy/motorcomm.c
+ *
+ * Driver for Motorcomm PHYs
+ *
+ * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
+ *
+ * Copyright (c) 2019 Motorcomm, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Support : Motorcomm Phys:
+ * Giga phys: yt8511, yt8521
+ * 100/10 Phys : yt8512, yt8512b, yt8510
+ * Automotive 100Mb Phys : yt8010
+ * Automotive 100/10 hyper range Phys: yt8510
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/motorcomm_phy.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+
+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
+{
+ int ret;
+ int val;
+
+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+ if (ret < 0)
+ return ret;
+
+ val = phy_read(phydev, REG_DEBUG_DATA);
+
+ return val;
+}
+
+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
+{
+ int ret;
+
+ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_write(phydev, REG_DEBUG_DATA, val);
+
+ return ret;
+}
+
+static int yt8010_config_aneg(struct phy_device *phydev)
+{
+ phydev->speed = SPEED_100;
+ return 0;
+}
+
+static int yt8512_clk_init(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
+ if (val < 0)
+ return val;
+
+ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
+
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
+ if (ret < 0)
+ return ret;
+
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
+ if (val < 0)
+ return val;
+
+ val |= YT8512_CONTROL1_RMII_EN;
+
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
+ if (ret < 0)
+ return ret;
+
+ val = phy_read(phydev, MII_BMCR);
+ if (val < 0)
+ return val;
+
+ val |= YT_SOFTWARE_RESET;
+ ret = phy_write(phydev, MII_BMCR, val);
+
+ return ret;
+}
+
+static int yt8512_led_init(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+ int mask;
+
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
+ if (val < 0)
+ return val;
+
+ val |= YT8512_LED0_ACT_BLK_IND;
+
+ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
+ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
+ YT8512_LED0_BT_ON_EN;
+ val &= ~mask;
+
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
+ if (ret < 0)
+ return ret;
+
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
+ if (val < 0)
+ return val;
+
+ val |= YT8512_LED1_BT_ON_EN;
+
+ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
+ val &= ~mask;
+
+ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
+
+ return ret;
+}
+
+static int yt8512_config_init(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+
+ ret = yt8512_clk_init(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = yt8512_led_init(phydev);
+
+ /* disable auto sleep */
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
+ if (val < 0)
+ return val;
+
+ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
+
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
+static int yt8512_read_status(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+ int speed, speed_mode, duplex;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+ if (val < 0)
+ return val;
+
+ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
+ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
+ switch (speed_mode) {
+ case 0:
+ speed = SPEED_10;
+ break;
+ case 1:
+ speed = SPEED_100;
+ break;
+ case 2:
+ case 3:
+ default:
+ speed = SPEED_UNKNOWN;
+ break;
+ }
+
+ phydev->speed = speed;
+ phydev->duplex = duplex;
+
+ return 0;
+}
+
+static int yt8521_config_init(struct phy_device *phydev)
+{
+ int ret;
+ int val;
+
+ /* disable auto sleep */
+ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
+ if (val < 0)
+ return val;
+
+ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
+ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
+ if (ret < 0)
+ return ret;
+
+ /* switch to access UTP */
+ ret = ytphy_write_ext(phydev, 0xa000, 0);
+ if (ret < 0)
+ return ret;
+
+ /* enable RXC clock when no wire plug */
+ val = ytphy_read_ext(phydev, 0xc);
+ if (val < 0)
+ return val;
+
+ val &= ~(1 << 12);
+ ret = ytphy_write_ext(phydev, 0xc, val);
+ if (ret < 0)
+ return ret;
+
+ /* output SyncE clock (125mhz) even link is down */
+ ret = ytphy_write_ext(phydev, 0xa012, 0x38);
+ if (ret < 0)
+ return ret;
+
+ /* disable rgmii clk 2ns delay */
+ val = ytphy_read_ext(phydev, 0xa001);
+ if (val < 0)
+ return val;
+
+ val &= ~(1 << 8);
+ ret = ytphy_write_ext(phydev, 0xa001, val);
+ if (ret < 0)
+ return ret;
+
+ /* setup delay */
+ val = (1 << 10) | (0xf << 4) | 5;
+ ret = ytphy_write_ext(phydev, 0xa003, val);
+ if (ret < 0)
+ return ret;
+
+ /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
+ ytphy_write_ext(phydev, 0xa00b, 0xe004);
+ ytphy_write_ext(phydev, 0xa00c, 0);
+ ytphy_write_ext(phydev, 0xa00d, 0x2600);
+ ytphy_write_ext(phydev, 0xa00e, 0x0070);
+ ytphy_write_ext(phydev, 0xa00f, 0x000a);
+
+ return 0;
+}
+
+static int yt8521_ack_interrupt(struct phy_device *phydev)
+{
+ int val;
+
+ val = phy_read(phydev, REG_INT_STATUS);
+ phydev_dbg(phydev, "intr status 0x04%x\n", val);
+
+ return (val < 0) ? val : 0;
+}
+
+static int yt8521_config_intr(struct phy_device *phydev)
+{
+ int val;
+ int err;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+ val = BIT(14) | BIT(13) | BIT(11) | BIT(10);
+ else
+ val = 0;
+
+ err = phy_write(phydev, REG_INT_MASK, val);
+ if (err)
+ return err;
+ err = yt8521_ack_interrupt(phydev);
+
+ return err;
+}
+
+static struct phy_driver ytphy_drvs[] = {
+ {
+ .phy_id = PHY_ID_YT8010,
+ .name = "YT8010 Automotive Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .config_aneg = yt8010_config_aneg,
+ .read_status = genphy_read_status,
+ }, {
+ .phy_id = PHY_ID_YT8510,
+ .name = "YT8510 100/10Mb Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .read_status = genphy_read_status,
+ }, {
+ .phy_id = PHY_ID_YT8511,
+ .name = "YT8511 Gigabit Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_GBIT_FEATURES,
+ .read_status = genphy_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ }, {
+ .phy_id = PHY_ID_YT8512,
+ .name = "YT8512 Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .config_init = yt8512_config_init,
+ .read_status = yt8512_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ }, {
+ .phy_id = PHY_ID_YT8512B,
+ .name = "YT8512B Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ .features = PHY_BASIC_FEATURES,
+ .config_init = yt8512_config_init,
+ .read_status = yt8512_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ }, {
+ .phy_id = PHY_ID_YT8521,
+ .name = "YT8521 Ethernet",
+ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
+ /* PHY_GBIT_FEATURES */
+ .config_init = yt8521_config_init,
+ .config_intr = yt8521_config_intr,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ },
+};
+
+module_phy_driver(ytphy_drvs);
+
+MODULE_DESCRIPTION("Motorcomm PHY driver");
+MODULE_AUTHOR("Leilei Zhao");
+MODULE_LICENSE("GPL");
+
+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
+ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
+ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h
new file mode 100644
index 000000000000..1e48c3671b69
--- /dev/null
+++ b/include/linux/motorcomm_phy.h
@@ -0,0 +1,67 @@
+/*
+ * include/linux/motorcomm_phy.h
+ *
+ * Motorcomm PHY IDs
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef _MOTORCOMM_PHY_H
+#define _MOTORCOMM_PHY_H
+
+#define MOTORCOMM_PHY_ID_MASK 0x00000fff
+
+#define PHY_ID_YT8010 0x00000309
+#define PHY_ID_YT8510 0x00000109
+#define PHY_ID_YT8511 0x0000010a
+#define PHY_ID_YT8512 0x00000118
+#define PHY_ID_YT8512B 0x00000128
+#define PHY_ID_YT8521 0x0000011a
+
+#define REG_PHY_SPEC_STATUS 0x11
+#define REG_INT_MASK 0x12
+#define REG_INT_STATUS 0x13
+#define REG_DEBUG_ADDR_OFFSET 0x1e
+#define REG_DEBUG_DATA 0x1f
+
+#define YT8512_EXTREG_AFE_PLL 0x50
+#define YT8512_EXTREG_EXTEND_COMBO 0x4000
+#define YT8512_EXTREG_LED0 0x40c0
+#define YT8512_EXTREG_LED1 0x40c3
+
+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
+
+#define YT_SOFTWARE_RESET 0x8000
+
+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
+#define YT8512_CONTROL1_RMII_EN 0x0001
+#define YT8512_LED0_ACT_BLK_IND 0x1000
+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
+#define YT8512_LED0_BT_BLK_EN 0x0002
+#define YT8512_LED0_HT_BLK_EN 0x0004
+#define YT8512_LED0_COL_BLK_EN 0x0008
+#define YT8512_LED0_BT_ON_EN 0x0010
+#define YT8512_LED1_BT_ON_EN 0x0010
+#define YT8512_LED1_TXACT_BLK_EN 0x0100
+#define YT8512_LED1_RXACT_BLK_EN 0x0200
+#define YT8512_SPEED_MODE 0xc000
+#define YT8512_DUPLEX 0x2000
+
+#define YT8512_SPEED_MODE_BIT 14
+#define YT8512_DUPLEX_BIT 13
+#define YT8512_EN_SLEEP_SW_BIT 15
+
+#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
+#define YT8521_EN_SLEEP_SW_BIT 15
+
+#define YT8521_SPEED_MODE 0xc000
+#define YT8521_DUPLEX 0x2000
+#define YT8521_SPEED_MODE_BIT 14
+#define YT8521_DUPLEX_BIT 13
+#define YT8521_LINK_STATUS_BIT 10
+
+#endif /* _MOTORCOMM_PHY_H */