diff --git a/config/boards/nanopi-r2c.conf b/config/boards/nanopi-r2c.conf new file mode 100644 index 0000000000..024b9affe9 --- /dev/null +++ b/config/boards/nanopi-r2c.conf @@ -0,0 +1,11 @@ +# Rockchip RK3328 quad core 1GB 2 x GBE USB2 +BOARD_NAME="Nanopi R2C" +BOARDFAMILY="rockchip64" +BOOTCONFIG="nanopi-r2s-rk3328_defconfig" +KERNEL_TARGET="current,edge" +DEFAULT_CONSOLE="serial" +MODULES="g_serial" +MODULES_BLACKLIST="rockchipdrm analogix_dp dw_mipi_dsi dw_hdmi gpu_sched lima hantro_vpu" +SERIALCON="ttyS2:1500000,ttyGS0" +BUILD_DESKTOP="no" +BOOT_FDT_FILE="rockchip/rk3328-nanopi-r2-rev06.dtb" diff --git a/config/kernel/linux-rockchip64-current.config b/config/kernel/linux-rockchip64-current.config index 25e106fe0d..4184f5b6ac 100644 --- a/config/kernel/linux-rockchip64-current.config +++ b/config/kernel/linux-rockchip64-current.config @@ -2908,6 +2908,7 @@ CONFIG_NATIONAL_PHY=m # CONFIG_NXP_TJA11XX_PHY is not set CONFIG_AT803X_PHY=m CONFIG_QSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=y CONFIG_REALTEK_PHY=m # CONFIG_RENESAS_PHY is not set CONFIG_ROCKCHIP_PHY=y diff --git a/config/sources/families/include/rockchip64_common.inc b/config/sources/families/include/rockchip64_common.inc index ccf7fbd2e2..4fc3d6efa5 100644 --- a/config/sources/families/include/rockchip64_common.inc +++ b/config/sources/families/include/rockchip64_common.inc @@ -38,7 +38,7 @@ else # rk3308, rk3328 fi -if [[ $BOARD == nanopi-r2s || $BOARD == nanopineo3 || $BOARD == orangepi-r1plus || $BOARD == renegade || $BOARD == rockpi-e || $BOARD == station-m1 || $BOARD == z28pro ]]; then +if [[ $BOARD == nanopi-r2s || $BOARD == nanopi-r2c || $BOARD == nanopineo3 || $BOARD == orangepi-r1plus || $BOARD == renegade || $BOARD == rockpi-e || $BOARD == station-m1 || $BOARD == z28pro ]]; then BOOT_USE_BLOBS=yes BOOT_SOC=rk3328 @@ -345,7 +345,7 @@ family_tweaks() chroot $SDCARD /bin/bash -c "systemctl --no-reload enable z28pro-bluetooth.service >/dev/null 2>&1" - elif [[ $BOARD == nanopi-r2s || $BOARD == orangepi-r1plus ]]; then + elif [[ $BOARD == nanopi-r2s || $BOARD == nanopi-r2c || $BOARD == orangepi-r1plus ]]; then # rename USB based network to lan0 mkdir -p $SDCARD/etc/udev/rules.d/ diff --git a/config/targets.conf b/config/targets.conf index daf8db9609..dac2e38dcb 100644 --- a/config/targets.conf +++ b/config/targets.conf @@ -336,6 +336,11 @@ nanopi-r2s current bullseye cli s nanopi-r2s current focal cli stable yes nanopi-r2s edge hirsute cli stable yes +# nanopi-r2c +nanopi-r2c current focal minimal stable yes +nanopi-r2c current buster cli stable yes +nanopi-r2c current bullseye cli stable yes +nanopi-r2c current focal cli stable yes # nanopi-r4s nanopi-r4s current focal minimal stable yes diff --git a/patch/kernel/archive/rockchip64-5.10/add-board-nanopi-r2c.patch b/patch/kernel/archive/rockchip64-5.10/add-board-nanopi-r2c.patch new file mode 100644 index 0000000000..298be847c1 --- /dev/null +++ b/patch/kernel/archive/rockchip64-5.10/add-board-nanopi-r2c.patch @@ -0,0 +1,95 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts +new file mode 100644 +index 000000000000..6322f59939b8 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts +@@ -0,0 +1,89 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++/dts-v1/; ++ ++#include "rk3328-nanopi-r2-rev00.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R2C"; ++ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; ++}; ++ ++&mach { ++ hwrev = <6>; ++ model = "NanoPi R2C"; ++}; ++ ++&rgmiim1_pins { ++ rockchip,pins = ++ /* mac_txclk */ ++ <1 RK_PB4 2 &pcfg_pull_none_8ma>, ++ /* mac_rxclk */ ++ <1 RK_PB5 2 &pcfg_pull_none>, ++ /* mac_mdio */ ++ <1 RK_PC3 2 &pcfg_pull_none_2ma>, ++ /* mac_txen */ ++ <1 RK_PD1 2 &pcfg_pull_none_8ma>, ++ /* mac_clk */ ++ <1 RK_PC5 2 &pcfg_pull_none_2ma>, ++ /* mac_rxdv */ ++ <1 RK_PC6 2 &pcfg_pull_none>, ++ /* mac_mdc */ ++ <1 RK_PC7 2 &pcfg_pull_none_2ma>, ++ /* mac_rxd1 */ ++ <1 RK_PB2 2 &pcfg_pull_none>, ++ /* mac_rxd0 */ ++ <1 RK_PB3 2 &pcfg_pull_none>, ++ /* mac_txd1 */ ++ <1 RK_PB0 2 &pcfg_pull_none_8ma>, ++ /* mac_txd0 */ ++ <1 RK_PB1 2 &pcfg_pull_none_8ma>, ++ /* mac_rxd3 */ ++ <1 RK_PB6 2 &pcfg_pull_none>, ++ /* mac_rxd2 */ ++ <1 RK_PB7 2 &pcfg_pull_none>, ++ /* mac_txd3 */ ++ <1 RK_PC0 2 &pcfg_pull_none_8ma>, ++ /* mac_txd2 */ ++ <1 RK_PC1 2 &pcfg_pull_none_8ma>, ++ ++ /* mac_txclk */ ++ <0 RK_PB0 1 &pcfg_pull_none>, ++ /* mac_txen */ ++ <0 RK_PB4 1 &pcfg_pull_none>, ++ /* mac_clk */ ++ <0 RK_PD0 1 &pcfg_pull_none>, ++ /* mac_txd1 */ ++ <0 RK_PC0 1 &pcfg_pull_none>, ++ /* mac_txd0 */ ++ <0 RK_PC1 1 &pcfg_pull_none>, ++ /* mac_txd3 */ ++ <0 RK_PC7 1 &pcfg_pull_none>, ++ /* mac_txd2 */ ++ <0 RK_PC6 1 &pcfg_pull_none>; ++}; ++ ++/delete-node/ &rtl8211e; ++ ++&gmac2io { ++ phy-handle = <ðphy3>; ++ snps,reset-delays-us = <0 15000 50000>; ++ tx_delay = <0x22>; ++ rx_delay = <0x12>; ++ mdio { ++ ++ ethphy3: ethernet-phy@3 { ++ compatible = "ethernet-phy-id0000.011a", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <3>; ++ interrupt-parent = <&gpio2>; ++ interrupts = ; ++ //reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ keep-clkout-on; ++ }; ++ }; ++}; diff --git a/patch/kernel/archive/rockchip64-5.10/add-boards-to-dts-makefile.patch b/patch/kernel/archive/rockchip64-5.10/add-boards-to-dts-makefile.patch index 9bf1b6b8e2..e64f967b8f 100644 --- a/patch/kernel/archive/rockchip64-5.10/add-boards-to-dts-makefile.patch +++ b/patch/kernel/archive/rockchip64-5.10/add-boards-to-dts-makefile.patch @@ -2,10 +2,11 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi index 26661c7b7..1462ed38b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -1,4 +1,18 @@ +@@ -1,4 +1,19 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev00.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev06.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev20.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3-rev02.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb diff --git a/patch/kernel/archive/rockchip64-5.10/net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch b/patch/kernel/archive/rockchip64-5.10/net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch new file mode 100644 index 0000000000..ca4283fde6 --- /dev/null +++ b/patch/kernel/archive/rockchip64-5.10/net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch @@ -0,0 +1,467 @@ +From 5d6862cc5eac1679d7a4ef388f7c9bbc70e76770 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Mon, 5 Jul 2021 17:03:00 +0800 +Subject: [PATCH] net: phy: Add driver for Motorcomm YT85xx PHYs + +Signed-off-by: hmz007 +--- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/motorcomm.c | 346 ++++++++++++++++++++++++++++++++++ + include/linux/motorcomm_phy.h | 68 +++++++ + 4 files changed, 420 insertions(+) + create mode 100644 drivers/net/phy/motorcomm.c + create mode 100644 include/linux/motorcomm_phy.h + +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index 698bea312adc..626ec44248dc 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -223,6 +223,11 @@ config MICROSEMI_PHY + help + Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs + ++config MOTORCOMM_PHY ++ tristate "Motorcomm PHYs" ++ help ++ Supports the YT8010, YT8510, YT8511, YT8512 PHYs. ++ + config NATIONAL_PHY + tristate "National Semiconductor PHYs" + help +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +index a13e402074cf..c99b00bc24b5 100644 +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -69,6 +69,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o + obj-$(CONFIG_MICROCHIP_PHY) += microchip.o + obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o + obj-$(CONFIG_MICROSEMI_PHY) += mscc/ ++obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o + obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o + obj-$(CONFIG_QSEMI_PHY) += qsemi.o +diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c +new file mode 100644 +index 000000000000..c53b5b88b226 +--- /dev/null ++++ b/drivers/net/phy/motorcomm.c +@@ -0,0 +1,345 @@ ++/* ++ * drivers/net/phy/motorcomm.c ++ * ++ * Driver for Motorcomm PHYs ++ * ++ * Author: Leilei Zhao ++ * ++ * Copyright (c) 2019 Motorcomm, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Support : Motorcomm Phys: ++ * Giga phys: yt8511, yt8521 ++ * 100/10 Phys : yt8512, yt8512b, yt8510 ++ * Automotive 100Mb Phys : yt8010 ++ * Automotive 100/10 hyper range Phys: yt8510 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) ++{ ++ int ret; ++ int val; ++ ++ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); ++ if (ret < 0) ++ return ret; ++ ++ val = phy_read(phydev, REG_DEBUG_DATA); ++ ++ return val; ++} ++ ++static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val) ++{ ++ int ret; ++ ++ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_write(phydev, REG_DEBUG_DATA, val); ++ ++ return ret; ++} ++ ++static int yt8010_config_aneg(struct phy_device *phydev) ++{ ++ phydev->speed = SPEED_100; ++ return 0; ++} ++ ++static int yt8512_clk_init(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL); ++ if (val < 0) ++ return val; ++ ++ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN; ++ ++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val); ++ if (ret < 0) ++ return ret; ++ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO); ++ if (val < 0) ++ return val; ++ ++ val |= YT8512_CONTROL1_RMII_EN; ++ ++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val); ++ if (ret < 0) ++ return ret; ++ ++ val = phy_read(phydev, MII_BMCR); ++ if (val < 0) ++ return val; ++ ++ val |= YT_SOFTWARE_RESET; ++ ret = phy_write(phydev, MII_BMCR, val); ++ ++ return ret; ++} ++ ++static int yt8512_led_init(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ int mask; ++ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0); ++ if (val < 0) ++ return val; ++ ++ val |= YT8512_LED0_ACT_BLK_IND; ++ ++ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN | ++ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN | ++ YT8512_LED0_BT_ON_EN; ++ val &= ~mask; ++ ++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val); ++ if (ret < 0) ++ return ret; ++ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1); ++ if (val < 0) ++ return val; ++ ++ val |= YT8512_LED1_BT_ON_EN; ++ ++ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN; ++ val &= ~mask; ++ ++ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val); ++ ++ return ret; ++} ++ ++static int yt8512_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ ++ ret = yt8512_clk_init(phydev); ++ if (ret < 0) ++ return ret; ++ ++ ret = yt8512_led_init(phydev); ++ ++ /* disable auto sleep */ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1); ++ if (val < 0) ++ return val; ++ ++ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT)); ++ ++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val); ++ if (ret < 0) ++ return ret; ++ ++ return ret; ++} ++ ++static int yt8512_read_status(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ int speed, speed_mode, duplex; ++ ++ ret = genphy_update_link(phydev); ++ if (ret) ++ return ret; ++ ++ val = phy_read(phydev, REG_PHY_SPEC_STATUS); ++ if (val < 0) ++ return val; ++ ++ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT; ++ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT; ++ switch (speed_mode) { ++ case 0: ++ speed = SPEED_10; ++ break; ++ case 1: ++ speed = SPEED_100; ++ break; ++ case 2: ++ case 3: ++ default: ++ speed = SPEED_UNKNOWN; ++ break; ++ } ++ ++ phydev->speed = speed; ++ phydev->duplex = duplex; ++ ++ return 0; ++} ++ ++static int yt8521_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ ++ /* disable auto sleep */ ++ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1); ++ if (val < 0) ++ return val; ++ ++ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT)); ++ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val); ++ if (ret < 0) ++ return ret; ++ ++ /* switch to access UTP */ ++ ret = ytphy_write_ext(phydev, 0xa000, 0); ++ if (ret < 0) ++ return ret; ++ ++ /* enable RXC clock when no wire plug */ ++ val = ytphy_read_ext(phydev, 0xc); ++ if (val < 0) ++ return val; ++ ++ val &= ~(1 << 12); ++ ret = ytphy_write_ext(phydev, 0xc, val); ++ if (ret < 0) ++ return ret; ++ ++ /* output SyncE clock (125mhz) even link is down */ ++ ret = ytphy_write_ext(phydev, 0xa012, 0x38); ++ if (ret < 0) ++ return ret; ++ ++ /* disable rgmii clk 2ns delay */ ++ val = ytphy_read_ext(phydev, 0xa001); ++ if (val < 0) ++ return val; ++ ++ val &= ~(1 << 8); ++ ret = ytphy_write_ext(phydev, 0xa001, val); ++ if (ret < 0) ++ return ret; ++ ++ /* setup delay */ ++ val = (1 << 10) | (0xf << 4) | 5; ++ ret = ytphy_write_ext(phydev, 0xa003, val); ++ if (ret < 0) ++ return ret; ++ ++ /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */ ++ ytphy_write_ext(phydev, 0xa00b, 0xe004); ++ ytphy_write_ext(phydev, 0xa00c, 0); ++ ytphy_write_ext(phydev, 0xa00d, 0x2600); ++ ytphy_write_ext(phydev, 0xa00e, 0x0070); ++ ytphy_write_ext(phydev, 0xa00f, 0x000a); ++ ++ return 0; ++} ++ ++static int yt8521_config_intr(struct phy_device *phydev) ++{ ++ int val; ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) ++ val = BIT(14) | BIT(13) | BIT(11) | BIT(10); ++ else ++ val = 0; ++ ++ return phy_write(phydev, REG_INT_MASK, val); ++} ++ ++static int yt8521_ack_interrupt(struct phy_device *phydev) ++{ ++ int val; ++ ++ val = phy_read(phydev, REG_INT_STATUS); ++ phydev_dbg(phydev, "intr status 0x04%x\n", val); ++ ++ return (val < 0) ? val : 0; ++} ++ ++static struct phy_driver ytphy_drvs[] = { ++ { ++ .phy_id = PHY_ID_YT8010, ++ .name = "YT8010 Automotive Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_BASIC_FEATURES, ++ .config_aneg = yt8010_config_aneg, ++ .read_status = genphy_read_status, ++ }, { ++ .phy_id = PHY_ID_YT8510, ++ .name = "YT8510 100/10Mb Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_BASIC_FEATURES, ++ .read_status = genphy_read_status, ++ }, { ++ .phy_id = PHY_ID_YT8511, ++ .name = "YT8511 Gigabit Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_GBIT_FEATURES, ++ .read_status = genphy_read_status, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, { ++ .phy_id = PHY_ID_YT8512, ++ .name = "YT8512 Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_BASIC_FEATURES, ++ .config_init = yt8512_config_init, ++ .read_status = yt8512_read_status, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, { ++ .phy_id = PHY_ID_YT8512B, ++ .name = "YT8512B Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_BASIC_FEATURES, ++ .config_init = yt8512_config_init, ++ .read_status = yt8512_read_status, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, { ++ .phy_id = PHY_ID_YT8521, ++ .name = "YT8521 Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ /* PHY_GBIT_FEATURES */ ++ .config_init = yt8521_config_init, ++ .ack_interrupt = yt8521_ack_interrupt, ++ .config_intr = yt8521_config_intr, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, ++}; ++ ++module_phy_driver(ytphy_drvs); ++ ++MODULE_DESCRIPTION("Motorcomm PHY driver"); ++MODULE_AUTHOR("Leilei Zhao"); ++MODULE_LICENSE("GPL"); ++ ++static struct mdio_device_id __maybe_unused motorcomm_tbl[] = { ++ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); +diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h +new file mode 100644 +index 000000000000..1e48c3671b69 +--- /dev/null ++++ b/include/linux/motorcomm_phy.h +@@ -0,0 +1,67 @@ ++/* ++ * include/linux/motorcomm_phy.h ++ * ++ * Motorcomm PHY IDs ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef _MOTORCOMM_PHY_H ++#define _MOTORCOMM_PHY_H ++ ++#define MOTORCOMM_PHY_ID_MASK 0x00000fff ++ ++#define PHY_ID_YT8010 0x00000309 ++#define PHY_ID_YT8510 0x00000109 ++#define PHY_ID_YT8511 0x0000010a ++#define PHY_ID_YT8512 0x00000118 ++#define PHY_ID_YT8512B 0x00000128 ++#define PHY_ID_YT8521 0x0000011a ++ ++#define REG_PHY_SPEC_STATUS 0x11 ++#define REG_INT_MASK 0x12 ++#define REG_INT_STATUS 0x13 ++#define REG_DEBUG_ADDR_OFFSET 0x1e ++#define REG_DEBUG_DATA 0x1f ++ ++#define YT8512_EXTREG_AFE_PLL 0x50 ++#define YT8512_EXTREG_EXTEND_COMBO 0x4000 ++#define YT8512_EXTREG_LED0 0x40c0 ++#define YT8512_EXTREG_LED1 0x40c3 ++ ++#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027 ++ ++#define YT_SOFTWARE_RESET 0x8000 ++ ++#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040 ++#define YT8512_CONTROL1_RMII_EN 0x0001 ++#define YT8512_LED0_ACT_BLK_IND 0x1000 ++#define YT8512_LED0_DIS_LED_AN_TRY 0x0001 ++#define YT8512_LED0_BT_BLK_EN 0x0002 ++#define YT8512_LED0_HT_BLK_EN 0x0004 ++#define YT8512_LED0_COL_BLK_EN 0x0008 ++#define YT8512_LED0_BT_ON_EN 0x0010 ++#define YT8512_LED1_BT_ON_EN 0x0010 ++#define YT8512_LED1_TXACT_BLK_EN 0x0100 ++#define YT8512_LED1_RXACT_BLK_EN 0x0200 ++#define YT8512_SPEED_MODE 0xc000 ++#define YT8512_DUPLEX 0x2000 ++ ++#define YT8512_SPEED_MODE_BIT 14 ++#define YT8512_DUPLEX_BIT 13 ++#define YT8512_EN_SLEEP_SW_BIT 15 ++ ++#define YT8521_EXTREG_SLEEP_CONTROL1 0x27 ++#define YT8521_EN_SLEEP_SW_BIT 15 ++ ++#define YT8521_SPEED_MODE 0xc000 ++#define YT8521_DUPLEX 0x2000 ++#define YT8521_SPEED_MODE_BIT 14 ++#define YT8521_DUPLEX_BIT 13 ++#define YT8521_LINK_STATUS_BIT 10 ++ ++#endif /* _MOTORCOMM_PHY_H */ diff --git a/patch/kernel/archive/rockchip64-5.14/add-board-nanopi-r2c.patch b/patch/kernel/archive/rockchip64-5.14/add-board-nanopi-r2c.patch new file mode 100644 index 0000000000..298be847c1 --- /dev/null +++ b/patch/kernel/archive/rockchip64-5.14/add-board-nanopi-r2c.patch @@ -0,0 +1,95 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts +new file mode 100644 +index 000000000000..6322f59939b8 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev06.dts +@@ -0,0 +1,89 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++/dts-v1/; ++ ++#include "rk3328-nanopi-r2-rev00.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R2C"; ++ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; ++}; ++ ++&mach { ++ hwrev = <6>; ++ model = "NanoPi R2C"; ++}; ++ ++&rgmiim1_pins { ++ rockchip,pins = ++ /* mac_txclk */ ++ <1 RK_PB4 2 &pcfg_pull_none_8ma>, ++ /* mac_rxclk */ ++ <1 RK_PB5 2 &pcfg_pull_none>, ++ /* mac_mdio */ ++ <1 RK_PC3 2 &pcfg_pull_none_2ma>, ++ /* mac_txen */ ++ <1 RK_PD1 2 &pcfg_pull_none_8ma>, ++ /* mac_clk */ ++ <1 RK_PC5 2 &pcfg_pull_none_2ma>, ++ /* mac_rxdv */ ++ <1 RK_PC6 2 &pcfg_pull_none>, ++ /* mac_mdc */ ++ <1 RK_PC7 2 &pcfg_pull_none_2ma>, ++ /* mac_rxd1 */ ++ <1 RK_PB2 2 &pcfg_pull_none>, ++ /* mac_rxd0 */ ++ <1 RK_PB3 2 &pcfg_pull_none>, ++ /* mac_txd1 */ ++ <1 RK_PB0 2 &pcfg_pull_none_8ma>, ++ /* mac_txd0 */ ++ <1 RK_PB1 2 &pcfg_pull_none_8ma>, ++ /* mac_rxd3 */ ++ <1 RK_PB6 2 &pcfg_pull_none>, ++ /* mac_rxd2 */ ++ <1 RK_PB7 2 &pcfg_pull_none>, ++ /* mac_txd3 */ ++ <1 RK_PC0 2 &pcfg_pull_none_8ma>, ++ /* mac_txd2 */ ++ <1 RK_PC1 2 &pcfg_pull_none_8ma>, ++ ++ /* mac_txclk */ ++ <0 RK_PB0 1 &pcfg_pull_none>, ++ /* mac_txen */ ++ <0 RK_PB4 1 &pcfg_pull_none>, ++ /* mac_clk */ ++ <0 RK_PD0 1 &pcfg_pull_none>, ++ /* mac_txd1 */ ++ <0 RK_PC0 1 &pcfg_pull_none>, ++ /* mac_txd0 */ ++ <0 RK_PC1 1 &pcfg_pull_none>, ++ /* mac_txd3 */ ++ <0 RK_PC7 1 &pcfg_pull_none>, ++ /* mac_txd2 */ ++ <0 RK_PC6 1 &pcfg_pull_none>; ++}; ++ ++/delete-node/ &rtl8211e; ++ ++&gmac2io { ++ phy-handle = <ðphy3>; ++ snps,reset-delays-us = <0 15000 50000>; ++ tx_delay = <0x22>; ++ rx_delay = <0x12>; ++ mdio { ++ ++ ethphy3: ethernet-phy@3 { ++ compatible = "ethernet-phy-id0000.011a", ++ "ethernet-phy-ieee802.3-c22"; ++ reg = <3>; ++ interrupt-parent = <&gpio2>; ++ interrupts = ; ++ //reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ keep-clkout-on; ++ }; ++ }; ++}; diff --git a/patch/kernel/archive/rockchip64-5.14/add-board-nanopi-r2s.patch b/patch/kernel/archive/rockchip64-5.14/add-board-nanopi-r2s.patch new file mode 100644 index 0000000000..563beecf56 --- /dev/null +++ b/patch/kernel/archive/rockchip64-5.14/add-board-nanopi-r2s.patch @@ -0,0 +1,1360 @@ +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi +new file mode 100644 +index 000000000..a3f5ff4bd +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi +@@ -0,0 +1,311 @@ ++/* ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++ ++/ { ++ ddr_timing: ddr_timing { ++ compatible = "rockchip,ddr-timing"; ++ ddr3_speed_bin = ; ++ ddr4_speed_bin = ; ++ pd_idle = <0>; ++ sr_idle = <0>; ++ sr_mc_gate_idle = <0>; ++ srpd_lite_idle = <0>; ++ standby_idle = <0>; ++ ++ auto_pd_dis_freq = <1066>; ++ auto_sr_dis_freq = <800>; ++ ddr3_dll_dis_freq = <300>; ++ ddr4_dll_dis_freq = <625>; ++ phy_dll_dis_freq = <400>; ++ ++ ddr3_odt_dis_freq = <100>; ++ phy_ddr3_odt_dis_freq = <100>; ++ ddr3_drv = ; ++ ddr3_odt = ; ++ phy_ddr3_ca_drv = ; ++ phy_ddr3_ck_drv = ; ++ phy_ddr3_dq_drv = ; ++ phy_ddr3_odt = ; ++ ++ lpddr3_odt_dis_freq = <666>; ++ phy_lpddr3_odt_dis_freq = <666>; ++ lpddr3_drv = ; ++ lpddr3_odt = ; ++ phy_lpddr3_ca_drv = ; ++ phy_lpddr3_ck_drv = ; ++ phy_lpddr3_dq_drv = ; ++ phy_lpddr3_odt = ; ++ ++ lpddr4_odt_dis_freq = <800>; ++ phy_lpddr4_odt_dis_freq = <800>; ++ lpddr4_drv = ; ++ lpddr4_dq_odt = ; ++ lpddr4_ca_odt = ; ++ phy_lpddr4_ca_drv = ; ++ phy_lpddr4_ck_cs_drv = ; ++ phy_lpddr4_dq_drv = ; ++ phy_lpddr4_odt = ; ++ ++ ddr4_odt_dis_freq = <666>; ++ phy_ddr4_odt_dis_freq = <666>; ++ ddr4_drv = ; ++ ddr4_odt = ; ++ phy_ddr4_ca_drv = ; ++ phy_ddr4_ck_drv = ; ++ phy_ddr4_dq_drv = ; ++ phy_ddr4_odt = ; ++ ++ /* CA de-skew, one step is 47.8ps, range 0-15 */ ++ ddr3a1_ddr4a9_de-skew = <7>; ++ ddr3a0_ddr4a10_de-skew = <7>; ++ ddr3a3_ddr4a6_de-skew = <8>; ++ ddr3a2_ddr4a4_de-skew = <8>; ++ ddr3a5_ddr4a8_de-skew = <7>; ++ ddr3a4_ddr4a5_de-skew = <9>; ++ ddr3a7_ddr4a11_de-skew = <7>; ++ ddr3a6_ddr4a7_de-skew = <9>; ++ ddr3a9_ddr4a0_de-skew = <8>; ++ ddr3a8_ddr4a13_de-skew = <7>; ++ ddr3a11_ddr4a3_de-skew = <9>; ++ ddr3a10_ddr4cs0_de-skew = <7>; ++ ddr3a13_ddr4a2_de-skew = <8>; ++ ddr3a12_ddr4ba1_de-skew = <7>; ++ ddr3a15_ddr4odt0_de-skew = <7>; ++ ddr3a14_ddr4a1_de-skew = <8>; ++ ddr3ba1_ddr4a15_de-skew = <7>; ++ ddr3ba0_ddr4bg0_de-skew = <7>; ++ ddr3ras_ddr4cke_de-skew = <7>; ++ ddr3ba2_ddr4ba0_de-skew = <8>; ++ ddr3we_ddr4bg1_de-skew = <8>; ++ ddr3cas_ddr4a12_de-skew = <7>; ++ ddr3ckn_ddr4ckn_de-skew = <8>; ++ ddr3ckp_ddr4ckp_de-skew = <8>; ++ ddr3cke_ddr4a16_de-skew = <8>; ++ ddr3odt0_ddr4a14_de-skew = <7>; ++ ddr3cs0_ddr4act_de-skew = <8>; ++ ddr3reset_ddr4reset_de-skew = <7>; ++ ddr3cs1_ddr4cs1_de-skew = <7>; ++ ddr3odt1_ddr4odt1_de-skew = <7>; ++ ++ /* DATA de-skew ++ * RX one step is 25.1ps, range 0-15 ++ * TX one step is 47.8ps, range 0-15 ++ */ ++ cs0_dm0_rx_de-skew = <7>; ++ cs0_dm0_tx_de-skew = <8>; ++ cs0_dq0_rx_de-skew = <7>; ++ cs0_dq0_tx_de-skew = <8>; ++ cs0_dq1_rx_de-skew = <7>; ++ cs0_dq1_tx_de-skew = <8>; ++ cs0_dq2_rx_de-skew = <7>; ++ cs0_dq2_tx_de-skew = <8>; ++ cs0_dq3_rx_de-skew = <7>; ++ cs0_dq3_tx_de-skew = <8>; ++ cs0_dq4_rx_de-skew = <7>; ++ cs0_dq4_tx_de-skew = <8>; ++ cs0_dq5_rx_de-skew = <7>; ++ cs0_dq5_tx_de-skew = <8>; ++ cs0_dq6_rx_de-skew = <7>; ++ cs0_dq6_tx_de-skew = <8>; ++ cs0_dq7_rx_de-skew = <7>; ++ cs0_dq7_tx_de-skew = <8>; ++ cs0_dqs0_rx_de-skew = <6>; ++ cs0_dqs0p_tx_de-skew = <9>; ++ cs0_dqs0n_tx_de-skew = <9>; ++ ++ cs0_dm1_rx_de-skew = <7>; ++ cs0_dm1_tx_de-skew = <7>; ++ cs0_dq8_rx_de-skew = <7>; ++ cs0_dq8_tx_de-skew = <8>; ++ cs0_dq9_rx_de-skew = <7>; ++ cs0_dq9_tx_de-skew = <7>; ++ cs0_dq10_rx_de-skew = <7>; ++ cs0_dq10_tx_de-skew = <8>; ++ cs0_dq11_rx_de-skew = <7>; ++ cs0_dq11_tx_de-skew = <7>; ++ cs0_dq12_rx_de-skew = <7>; ++ cs0_dq12_tx_de-skew = <8>; ++ cs0_dq13_rx_de-skew = <7>; ++ cs0_dq13_tx_de-skew = <7>; ++ cs0_dq14_rx_de-skew = <7>; ++ cs0_dq14_tx_de-skew = <8>; ++ cs0_dq15_rx_de-skew = <7>; ++ cs0_dq15_tx_de-skew = <7>; ++ cs0_dqs1_rx_de-skew = <7>; ++ cs0_dqs1p_tx_de-skew = <9>; ++ cs0_dqs1n_tx_de-skew = <9>; ++ ++ cs0_dm2_rx_de-skew = <7>; ++ cs0_dm2_tx_de-skew = <8>; ++ cs0_dq16_rx_de-skew = <7>; ++ cs0_dq16_tx_de-skew = <8>; ++ cs0_dq17_rx_de-skew = <7>; ++ cs0_dq17_tx_de-skew = <8>; ++ cs0_dq18_rx_de-skew = <7>; ++ cs0_dq18_tx_de-skew = <8>; ++ cs0_dq19_rx_de-skew = <7>; ++ cs0_dq19_tx_de-skew = <8>; ++ cs0_dq20_rx_de-skew = <7>; ++ cs0_dq20_tx_de-skew = <8>; ++ cs0_dq21_rx_de-skew = <7>; ++ cs0_dq21_tx_de-skew = <8>; ++ cs0_dq22_rx_de-skew = <7>; ++ cs0_dq22_tx_de-skew = <8>; ++ cs0_dq23_rx_de-skew = <7>; ++ cs0_dq23_tx_de-skew = <8>; ++ cs0_dqs2_rx_de-skew = <6>; ++ cs0_dqs2p_tx_de-skew = <9>; ++ cs0_dqs2n_tx_de-skew = <9>; ++ ++ cs0_dm3_rx_de-skew = <7>; ++ cs0_dm3_tx_de-skew = <7>; ++ cs0_dq24_rx_de-skew = <7>; ++ cs0_dq24_tx_de-skew = <8>; ++ cs0_dq25_rx_de-skew = <7>; ++ cs0_dq25_tx_de-skew = <7>; ++ cs0_dq26_rx_de-skew = <7>; ++ cs0_dq26_tx_de-skew = <7>; ++ cs0_dq27_rx_de-skew = <7>; ++ cs0_dq27_tx_de-skew = <7>; ++ cs0_dq28_rx_de-skew = <7>; ++ cs0_dq28_tx_de-skew = <7>; ++ cs0_dq29_rx_de-skew = <7>; ++ cs0_dq29_tx_de-skew = <7>; ++ cs0_dq30_rx_de-skew = <7>; ++ cs0_dq30_tx_de-skew = <7>; ++ cs0_dq31_rx_de-skew = <7>; ++ cs0_dq31_tx_de-skew = <7>; ++ cs0_dqs3_rx_de-skew = <7>; ++ cs0_dqs3p_tx_de-skew = <9>; ++ cs0_dqs3n_tx_de-skew = <9>; ++ ++ cs1_dm0_rx_de-skew = <7>; ++ cs1_dm0_tx_de-skew = <8>; ++ cs1_dq0_rx_de-skew = <7>; ++ cs1_dq0_tx_de-skew = <8>; ++ cs1_dq1_rx_de-skew = <7>; ++ cs1_dq1_tx_de-skew = <8>; ++ cs1_dq2_rx_de-skew = <7>; ++ cs1_dq2_tx_de-skew = <8>; ++ cs1_dq3_rx_de-skew = <7>; ++ cs1_dq3_tx_de-skew = <8>; ++ cs1_dq4_rx_de-skew = <7>; ++ cs1_dq4_tx_de-skew = <8>; ++ cs1_dq5_rx_de-skew = <7>; ++ cs1_dq5_tx_de-skew = <8>; ++ cs1_dq6_rx_de-skew = <7>; ++ cs1_dq6_tx_de-skew = <8>; ++ cs1_dq7_rx_de-skew = <7>; ++ cs1_dq7_tx_de-skew = <8>; ++ cs1_dqs0_rx_de-skew = <6>; ++ cs1_dqs0p_tx_de-skew = <9>; ++ cs1_dqs0n_tx_de-skew = <9>; ++ ++ cs1_dm1_rx_de-skew = <7>; ++ cs1_dm1_tx_de-skew = <7>; ++ cs1_dq8_rx_de-skew = <7>; ++ cs1_dq8_tx_de-skew = <8>; ++ cs1_dq9_rx_de-skew = <7>; ++ cs1_dq9_tx_de-skew = <7>; ++ cs1_dq10_rx_de-skew = <7>; ++ cs1_dq10_tx_de-skew = <8>; ++ cs1_dq11_rx_de-skew = <7>; ++ cs1_dq11_tx_de-skew = <7>; ++ cs1_dq12_rx_de-skew = <7>; ++ cs1_dq12_tx_de-skew = <8>; ++ cs1_dq13_rx_de-skew = <7>; ++ cs1_dq13_tx_de-skew = <7>; ++ cs1_dq14_rx_de-skew = <7>; ++ cs1_dq14_tx_de-skew = <8>; ++ cs1_dq15_rx_de-skew = <7>; ++ cs1_dq15_tx_de-skew = <7>; ++ cs1_dqs1_rx_de-skew = <7>; ++ cs1_dqs1p_tx_de-skew = <9>; ++ cs1_dqs1n_tx_de-skew = <9>; ++ ++ cs1_dm2_rx_de-skew = <7>; ++ cs1_dm2_tx_de-skew = <8>; ++ cs1_dq16_rx_de-skew = <7>; ++ cs1_dq16_tx_de-skew = <8>; ++ cs1_dq17_rx_de-skew = <7>; ++ cs1_dq17_tx_de-skew = <8>; ++ cs1_dq18_rx_de-skew = <7>; ++ cs1_dq18_tx_de-skew = <8>; ++ cs1_dq19_rx_de-skew = <7>; ++ cs1_dq19_tx_de-skew = <8>; ++ cs1_dq20_rx_de-skew = <7>; ++ cs1_dq20_tx_de-skew = <8>; ++ cs1_dq21_rx_de-skew = <7>; ++ cs1_dq21_tx_de-skew = <8>; ++ cs1_dq22_rx_de-skew = <7>; ++ cs1_dq22_tx_de-skew = <8>; ++ cs1_dq23_rx_de-skew = <7>; ++ cs1_dq23_tx_de-skew = <8>; ++ cs1_dqs2_rx_de-skew = <6>; ++ cs1_dqs2p_tx_de-skew = <9>; ++ cs1_dqs2n_tx_de-skew = <9>; ++ ++ cs1_dm3_rx_de-skew = <7>; ++ cs1_dm3_tx_de-skew = <7>; ++ cs1_dq24_rx_de-skew = <7>; ++ cs1_dq24_tx_de-skew = <8>; ++ cs1_dq25_rx_de-skew = <7>; ++ cs1_dq25_tx_de-skew = <7>; ++ cs1_dq26_rx_de-skew = <7>; ++ cs1_dq26_tx_de-skew = <7>; ++ cs1_dq27_rx_de-skew = <7>; ++ cs1_dq27_tx_de-skew = <7>; ++ cs1_dq28_rx_de-skew = <7>; ++ cs1_dq28_tx_de-skew = <7>; ++ cs1_dq29_rx_de-skew = <7>; ++ cs1_dq29_tx_de-skew = <7>; ++ cs1_dq30_rx_de-skew = <7>; ++ cs1_dq30_tx_de-skew = <7>; ++ cs1_dq31_rx_de-skew = <7>; ++ cs1_dq31_tx_de-skew = <7>; ++ cs1_dqs3_rx_de-skew = <7>; ++ cs1_dqs3p_tx_de-skew = <9>; ++ cs1_dqs3n_tx_de-skew = <9>; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi +new file mode 100644 +index 000000000..36890bb7f +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-common.dtsi +@@ -0,0 +1,625 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd ++ */ ++ ++/dts-v1/; ++#include "rk3328-dram-default-timing.dtsi" ++#include "rk3328.dtsi" ++ ++/ { ++ model = "FriendlyElec boards based on Rockchip RK3328"; ++ compatible = "friendlyelec,nanopi-r2", ++ "rockchip,rk3328"; ++ ++ aliases { ++ ethernet1 = &r8153; ++ }; ++ ++ chosen { ++ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0"; ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clkin: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ mach: board { ++ compatible = "friendlyelec,board"; ++ machine = "NANOPI-R2"; ++ hwrev = <255>; ++ model = "NanoPi R2 Series"; ++ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; ++ nvmem-cell-names = "id", "cpu-version"; ++ }; ++ ++ leds: gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 =<&leds_gpio>; ++ status = "disabled"; ++ ++ led@1 { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "status_led"; ++ linux,default-trigger = "heartbeat"; ++ linux,default-trigger-delay-ms = <0>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk805 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sdmmc_ext: dwmmc@ff5f0000 { ++ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xff5f0000 0x0 0x4000>; ++ clock-freq-min-max = <400000 150000000>; ++ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, ++ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; ++ fifo-depth = <0x100>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0m1_pin>; ++ regulator-boot-on; ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vccio_sd: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ regulator-name = "vccio_sd"; ++ regulator-type = "voltage"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <&vcc_io>; ++ startup-delay-us = <2000>; ++ regulator-settling-time-us = <5000>; ++ enable-active-high; ++ status = "disabled"; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_phy: vcc-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_phy"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc_host_vbus: host-vbus-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_host_vbus"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ dfi: dfi@ff790000 { ++ reg = <0x00 0xff790000 0x00 0x400>; ++ compatible = "rockchip,rk3328-dfi"; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ ++ dmc: dmc { ++ compatible = "rockchip,rk3328-dmc"; ++ devfreq-events = <&dfi>; ++ clocks = <&cru SCLK_DDRCLK>; ++ clock-names = "dmc_clk"; ++ operating-points-v2 = <&dmc_opp_table>; ++ ddr_timing = <&ddr_timing>; ++ upthreshold = <40>; ++ downdifferential = <20>; ++ auto-min-freq = <786000>; ++ auto-freq-en = <0>; ++ #cooling-cells = <2>; ++ status = "disabled"; ++ ++ ddr_power_model: ddr_power_model { ++ compatible = "ddr_power_model"; ++ dynamic-power-coefficient = <120>; ++ static-power-coefficient = <200>; ++ ts = <32000 4700 (-80) 2>; ++ thermal-zone = "soc-thermal"; ++ }; ++ }; ++ ++ dmc_opp_table: dmc-opp-table { ++ compatible = "operating-points-v2"; ++ ++ rockchip,leakage-voltage-sel = < ++ 1 10 0 ++ 11 254 1 ++ >; ++ nvmem-cells = <&logic_leakage>; ++ nvmem-cell-names = "ddr_leakage"; ++ ++ opp-786000000 { ++ opp-hz = /bits/ 64 <786000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <1050000>; ++ }; ++ opp-798000000 { ++ opp-hz = /bits/ 64 <798000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <1050000>; ++ }; ++ opp-840000000 { ++ opp-hz = /bits/ 64 <840000000>; ++ opp-microvolt = <1075000>; ++ opp-microvolt-L0 = <1075000>; ++ opp-microvolt-L1 = <1050000>; ++ }; ++ opp-924000000 { ++ opp-hz = /bits/ 64 <924000000>; ++ opp-microvolt = <1100000>; ++ opp-microvolt-L0 = <1100000>; ++ opp-microvolt-L1 = <1075000>; ++ }; ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1175000>; ++ opp-microvolt-L0 = <1175000>; ++ opp-microvolt-L1 = <1150000>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&dfi { ++ status = "okay"; ++}; ++ ++&dmc { ++ center-supply = <&vdd_logic>; ++ status = "okay"; ++}; ++ ++&emmc { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <150000000>; ++ mmc-hs200-1_8v; ++ no-sd; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; ++ vmmc-supply = <&vcc_io>; ++ vqmmc-supply = <&vcc18_emmc>; ++ status = "okay"; ++}; ++ ++&gmac2phy { ++ phy-supply = <&vcc_phy>; ++ clock_in_out = "output"; ++ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; ++ assigned-clock-rate = <50000000>; ++ assigned-clocks = <&cru SCLK_MAC2PHY>; ++ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; ++ status = "disabled"; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ clock_in_out = "input"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmiim1_pins>; ++ phy-handle = <&rtl8211e>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc_phy>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 30000>; ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,aal; ++ snps,rxpbl = <0x4>; ++ snps,txpbl = <0x4>; ++ tx_delay = <0x24>; ++ rx_delay = <0x18>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211e: phy@0 { ++ reg = <0>; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <30000>; ++ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */ ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: rk805@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_io>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-init-microvolt = <1075000>; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-init-microvolt = <1225000>; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_18>; ++ pmuio-supply = <&vcc_io>; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc0 { ++ sdmmc0_clk: sdmmc0-clk { ++ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; ++ }; ++ ++ sdmmc0_cmd: sdmmc0-cmd { ++ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; ++ }; ++ ++ sdmmc0_dectn: sdmmc0-dectn { ++ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; ++ }; ++ ++ sdmmc0_bus4: sdmmc0-bus4 { ++ rockchip,pins = ++ <1 RK_PA0 1 &pcfg_pull_up_4ma>, ++ <1 RK_PA1 1 &pcfg_pull_up_4ma>, ++ <1 RK_PA2 1 &pcfg_pull_up_4ma>, ++ <1 RK_PA3 1 &pcfg_pull_up_4ma>; ++ }; ++ }; ++ ++ sdmmc0ext { ++ sdmmc0ext_clk: sdmmc0ext-clk { ++ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>; ++ }; ++ ++ sdmmc0ext_cmd: sdmmc0ext-cmd { ++ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>; ++ }; ++ ++ sdmmc0ext_bus4: sdmmc0ext-bus4 { ++ rockchip,pins = ++ <3 RK_PA4 3 &pcfg_pull_up_2ma>, ++ <3 RK_PA5 3 &pcfg_pull_up_2ma>, ++ <3 RK_PA6 3 &pcfg_pull_up_2ma>, ++ <3 RK_PA7 3 &pcfg_pull_up_2ma>; ++ }; ++ }; ++ ++ gmac-1 { ++ rgmiim1_pins: rgmiim1-pins { ++ rockchip,pins = ++ /* mac_txclk */ ++ <1 RK_PB4 2 &pcfg_pull_none_4ma>, ++ /* mac_rxclk */ ++ <1 RK_PB5 2 &pcfg_pull_none>, ++ /* mac_mdio */ ++ <1 RK_PC3 2 &pcfg_pull_none_2ma>, ++ /* mac_txen */ ++ <1 RK_PD1 2 &pcfg_pull_none_4ma>, ++ /* mac_clk */ ++ <1 RK_PC5 2 &pcfg_pull_none_2ma>, ++ /* mac_rxdv */ ++ <1 RK_PC6 2 &pcfg_pull_none>, ++ /* mac_mdc */ ++ <1 RK_PC7 2 &pcfg_pull_none_2ma>, ++ /* mac_rxd1 */ ++ <1 RK_PB2 2 &pcfg_pull_none>, ++ /* mac_rxd0 */ ++ <1 RK_PB3 2 &pcfg_pull_none>, ++ /* mac_txd1 */ ++ <1 RK_PB0 2 &pcfg_pull_none_4ma>, ++ /* mac_txd0 */ ++ <1 RK_PB1 2 &pcfg_pull_none_4ma>, ++ /* mac_rxd3 */ ++ <1 RK_PB6 2 &pcfg_pull_none>, ++ /* mac_rxd2 */ ++ <1 RK_PB7 2 &pcfg_pull_none>, ++ /* mac_txd3 */ ++ <1 RK_PC0 2 &pcfg_pull_none_4ma>, ++ /* mac_txd2 */ ++ <1 RK_PC1 2 &pcfg_pull_none_4ma>, ++ ++ /* mac_txclk */ ++ <0 RK_PB0 1 &pcfg_pull_none>, ++ /* mac_txen */ ++ <0 RK_PB4 1 &pcfg_pull_none>, ++ /* mac_clk */ ++ <0 RK_PD0 1 &pcfg_pull_none>, ++ /* mac_txd1 */ ++ <0 RK_PC0 1 &pcfg_pull_none>, ++ /* mac_txd0 */ ++ <0 RK_PC1 1 &pcfg_pull_none>, ++ /* mac_txd3 */ ++ <0 RK_PC7 1 &pcfg_pull_none>, ++ /* mac_txd2 */ ++ <0 RK_PC6 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ host_vbus_drv: host-vbus-drv { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ otg_vbus_drv: otg-vbus-drv { ++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ gpio-leds { ++ leds_gpio: leds-gpio { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ vmmc-supply = <&vcc_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc_ext { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ disable-wp; ++ keep-power-in-suspend; ++ max-frequency = <100000000>; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ num-slots = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>; ++ rockchip,default-sample-phase = <120>; ++ supports-sdio; ++ sd-uhs-sdr104; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++&usb20_otg { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++ ++ ++ ++ ++&usbdrd3 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dr_mode = "host"; ++ r8153: device@2 { ++ compatible = "usbbda,8153"; ++ reg = <2>; ++ local-mac-address = [00 00 00 00 00 00]; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts +new file mode 100644 +index 000000000..971397659 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev00.dts +@@ -0,0 +1,127 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++/dts-v1/; ++#include ++#include "rk3328-nanopi-r2-common.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R2S"; ++ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ autorepeat; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio_key1>; ++ ++ button@0 { ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ linux,input-type = <1>; ++ gpio-key,wakeup = <1>; ++ debounce-interval = <100>; ++ }; ++ }; ++ ++ vcc_rtl8153: vcc-rtl8153-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb30_en_drv>; ++ regulator-always-on; ++ regulator-name = "vcc_rtl8153"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ off-on-delay-us = <5000>; ++ enable-active-high; ++ }; ++}; ++ ++&mach { ++ hwrev = <0>; ++ model = "NanoPi R2S"; ++}; ++ ++&emmc { ++ status = "disabled"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++}; ++ ++&leds { ++ status = "okay"; ++ ++ led@2 { ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ label = "lan_led"; ++ }; ++ ++ led@3 { ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ label = "wan_led"; ++ linux,default-trigger = "stmmac-0:00:link"; ++ }; ++}; ++ ++&rk805 { ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++}; ++ ++&vccio_sd { ++ status = "okay"; ++}; ++ ++&io_domains { ++ vccio3-supply = <&vccio_sd>; ++}; ++ ++&sdmmc { ++ vqmmc-supply = <&vccio_sd>; ++ max-frequency = <150000000>; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&sdmmc_ext { ++ status = "disabled"; ++}; ++ ++&sdio_pwrseq { ++ status = "disabled"; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ gpio_key1: gpio-key1 { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ otg_vbus_drv: otg-vbus-drv { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usb30_en_drv: usb30-en-drv { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev20.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev20.dts +new file mode 100644 +index 000000000..5663ce078 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2-rev20.dts +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++/dts-v1/; ++#include "rk3328-nanopi-r2-common.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R2"; ++ compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; ++}; ++ ++&mach { ++ hwrev = <0x20>; ++ model = "NanoPi R2"; ++}; ++ ++&gmac2io { ++ pinctrl-0 = <&rgmiim1_pins>, <&phy_intb>, <&phy_rstb>; ++}; ++ ++&rtl8211e { ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++}; ++ ++&pinctrl { ++ phy { ++ phy_intb: phy-intb { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ phy_rstb: phy-rstb { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h +new file mode 100644 +index 000000000..b065432e7 +--- /dev/null ++++ b/include/dt-bindings/clock/rockchip-ddr.h +@@ -0,0 +1,63 @@ ++/* ++ * ++ * Copyright (C) 2017 ROCKCHIP, Inc. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H ++#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H ++ ++#define DDR2_DEFAULT (0) ++ ++#define DDR3_800D (0) /* 5-5-5 */ ++#define DDR3_800E (1) /* 6-6-6 */ ++#define DDR3_1066E (2) /* 6-6-6 */ ++#define DDR3_1066F (3) /* 7-7-7 */ ++#define DDR3_1066G (4) /* 8-8-8 */ ++#define DDR3_1333F (5) /* 7-7-7 */ ++#define DDR3_1333G (6) /* 8-8-8 */ ++#define DDR3_1333H (7) /* 9-9-9 */ ++#define DDR3_1333J (8) /* 10-10-10 */ ++#define DDR3_1600G (9) /* 8-8-8 */ ++#define DDR3_1600H (10) /* 9-9-9 */ ++#define DDR3_1600J (11) /* 10-10-10 */ ++#define DDR3_1600K (12) /* 11-11-11 */ ++#define DDR3_1866J (13) /* 10-10-10 */ ++#define DDR3_1866K (14) /* 11-11-11 */ ++#define DDR3_1866L (15) /* 12-12-12 */ ++#define DDR3_1866M (16) /* 13-13-13 */ ++#define DDR3_2133K (17) /* 11-11-11 */ ++#define DDR3_2133L (18) /* 12-12-12 */ ++#define DDR3_2133M (19) /* 13-13-13 */ ++#define DDR3_2133N (20) /* 14-14-14 */ ++#define DDR3_DEFAULT (21) ++#define DDR_DDR2 (22) ++#define DDR_LPDDR (23) ++#define DDR_LPDDR2 (24) ++ ++#define DDR4_1600J (0) /* 10-10-10 */ ++#define DDR4_1600K (1) /* 11-11-11 */ ++#define DDR4_1600L (2) /* 12-12-12 */ ++#define DDR4_1866L (3) /* 12-12-12 */ ++#define DDR4_1866M (4) /* 13-13-13 */ ++#define DDR4_1866N (5) /* 14-14-14 */ ++#define DDR4_2133N (6) /* 14-14-14 */ ++#define DDR4_2133P (7) /* 15-15-15 */ ++#define DDR4_2133R (8) /* 16-16-16 */ ++#define DDR4_2400P (9) /* 15-15-15 */ ++#define DDR4_2400R (10) /* 16-16-16 */ ++#define DDR4_2400U (11) /* 18-18-18 */ ++#define DDR4_DEFAULT (12) ++ ++#define PAUSE_CPU_STACK_SIZE 16 ++ ++#endif +diff --git a/include/dt-bindings/memory/rk3328-dram.h b/include/dt-bindings/memory/rk3328-dram.h +new file mode 100644 +index 000000000..171f41c25 +--- /dev/null ++++ b/include/dt-bindings/memory/rk3328-dram.h +@@ -0,0 +1,159 @@ ++/* ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H ++#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H ++ ++#define DDR3_DS_34ohm (34) ++#define DDR3_DS_40ohm (40) ++ ++#define DDR3_ODT_DIS (0) ++#define DDR3_ODT_40ohm (40) ++#define DDR3_ODT_60ohm (60) ++#define DDR3_ODT_120ohm (120) ++ ++#define LP2_DS_34ohm (34) ++#define LP2_DS_40ohm (40) ++#define LP2_DS_48ohm (48) ++#define LP2_DS_60ohm (60) ++#define LP2_DS_68_6ohm (68) /* optional */ ++#define LP2_DS_80ohm (80) ++#define LP2_DS_120ohm (120) /* optional */ ++ ++#define LP3_DS_34ohm (34) ++#define LP3_DS_40ohm (40) ++#define LP3_DS_48ohm (48) ++#define LP3_DS_60ohm (60) ++#define LP3_DS_80ohm (80) ++#define LP3_DS_34D_40U (3440) ++#define LP3_DS_40D_48U (4048) ++#define LP3_DS_34D_48U (3448) ++ ++#define LP3_ODT_DIS (0) ++#define LP3_ODT_60ohm (60) ++#define LP3_ODT_120ohm (120) ++#define LP3_ODT_240ohm (240) ++ ++#define LP4_PDDS_40ohm (40) ++#define LP4_PDDS_48ohm (48) ++#define LP4_PDDS_60ohm (60) ++#define LP4_PDDS_80ohm (80) ++#define LP4_PDDS_120ohm (120) ++#define LP4_PDDS_240ohm (240) ++ ++#define LP4_DQ_ODT_40ohm (40) ++#define LP4_DQ_ODT_48ohm (48) ++#define LP4_DQ_ODT_60ohm (60) ++#define LP4_DQ_ODT_80ohm (80) ++#define LP4_DQ_ODT_120ohm (120) ++#define LP4_DQ_ODT_240ohm (240) ++#define LP4_DQ_ODT_DIS (0) ++ ++#define LP4_CA_ODT_40ohm (40) ++#define LP4_CA_ODT_48ohm (48) ++#define LP4_CA_ODT_60ohm (60) ++#define LP4_CA_ODT_80ohm (80) ++#define LP4_CA_ODT_120ohm (120) ++#define LP4_CA_ODT_240ohm (240) ++#define LP4_CA_ODT_DIS (0) ++ ++#define DDR4_DS_34ohm (34) ++#define DDR4_DS_48ohm (48) ++#define DDR4_RTT_NOM_DIS (0) ++#define DDR4_RTT_NOM_60ohm (60) ++#define DDR4_RTT_NOM_120ohm (120) ++#define DDR4_RTT_NOM_40ohm (40) ++#define DDR4_RTT_NOM_240ohm (240) ++#define DDR4_RTT_NOM_48ohm (48) ++#define DDR4_RTT_NOM_80ohm (80) ++#define DDR4_RTT_NOM_34ohm (34) ++ ++#define PHY_DDR3_RON_RTT_DISABLE (0) ++#define PHY_DDR3_RON_RTT_451ohm (1) ++#define PHY_DDR3_RON_RTT_225ohm (2) ++#define PHY_DDR3_RON_RTT_150ohm (3) ++#define PHY_DDR3_RON_RTT_112ohm (4) ++#define PHY_DDR3_RON_RTT_90ohm (5) ++#define PHY_DDR3_RON_RTT_75ohm (6) ++#define PHY_DDR3_RON_RTT_64ohm (7) ++#define PHY_DDR3_RON_RTT_56ohm (16) ++#define PHY_DDR3_RON_RTT_50ohm (17) ++#define PHY_DDR3_RON_RTT_45ohm (18) ++#define PHY_DDR3_RON_RTT_41ohm (19) ++#define PHY_DDR3_RON_RTT_37ohm (20) ++#define PHY_DDR3_RON_RTT_34ohm (21) ++#define PHY_DDR3_RON_RTT_33ohm (22) ++#define PHY_DDR3_RON_RTT_30ohm (23) ++#define PHY_DDR3_RON_RTT_28ohm (24) ++#define PHY_DDR3_RON_RTT_26ohm (25) ++#define PHY_DDR3_RON_RTT_25ohm (26) ++#define PHY_DDR3_RON_RTT_23ohm (27) ++#define PHY_DDR3_RON_RTT_22ohm (28) ++#define PHY_DDR3_RON_RTT_21ohm (29) ++#define PHY_DDR3_RON_RTT_20ohm (30) ++#define PHY_DDR3_RON_RTT_19ohm (31) ++ ++#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) ++#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) ++#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) ++#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) ++#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) ++#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) ++#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) ++#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) ++#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) ++#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) ++#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) ++#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) ++#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) ++#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) ++#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) ++#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) ++#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) ++#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) ++#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) ++#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) ++#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) ++#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) ++#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) ++#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) ++ ++#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/ diff --git a/patch/kernel/archive/rockchip64-5.14/add-boards-to-dts-makefile.patch b/patch/kernel/archive/rockchip64-5.14/add-boards-to-dts-makefile.patch index bdbad884ec..e6acdf5472 100644 --- a/patch/kernel/archive/rockchip64-5.14/add-boards-to-dts-makefile.patch +++ b/patch/kernel/archive/rockchip64-5.14/add-boards-to-dts-makefile.patch @@ -2,11 +2,14 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi index 26661c7b7..1462ed38b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -1,4 +1,15 @@ +@@ -1,4 +1,18 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev00.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev06.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev20.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-z28pro.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb diff --git a/patch/kernel/archive/rockchip64-5.14/net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch b/patch/kernel/archive/rockchip64-5.14/net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch new file mode 100644 index 0000000000..715ced3388 --- /dev/null +++ b/patch/kernel/archive/rockchip64-5.14/net-phy-Add-driver-for-Motorcomm-YT85xx-PHYs.patch @@ -0,0 +1,457 @@ +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index 698bea312adc..626ec44248dc 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -223,6 +223,11 @@ config MICROSEMI_PHY + help + Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs + ++config MOTORCOMM_PHY ++ tristate "Motorcomm PHYs" ++ help ++ Supports the YT8010, YT8510, YT8511, YT8512 PHYs. ++ + config NATIONAL_PHY + tristate "National Semiconductor PHYs" + help +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +index a13e402074cf..c99b00bc24b5 100644 +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -69,6 +69,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o + obj-$(CONFIG_MICROCHIP_PHY) += microchip.o + obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o + obj-$(CONFIG_MICROSEMI_PHY) += mscc/ ++obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o + obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o + obj-$(CONFIG_QSEMI_PHY) += qsemi.o +diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c +new file mode 100644 +index 000000000000..c53b5b88b226 +--- /dev/null ++++ b/drivers/net/phy/motorcomm.c +@@ -0,0 +1,350 @@ ++/* ++ * drivers/net/phy/motorcomm.c ++ * ++ * Driver for Motorcomm PHYs ++ * ++ * Author: Leilei Zhao ++ * ++ * Copyright (c) 2019 Motorcomm, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Support : Motorcomm Phys: ++ * Giga phys: yt8511, yt8521 ++ * 100/10 Phys : yt8512, yt8512b, yt8510 ++ * Automotive 100Mb Phys : yt8010 ++ * Automotive 100/10 hyper range Phys: yt8510 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ytphy_read_ext(struct phy_device *phydev, u32 regnum) ++{ ++ int ret; ++ int val; ++ ++ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); ++ if (ret < 0) ++ return ret; ++ ++ val = phy_read(phydev, REG_DEBUG_DATA); ++ ++ return val; ++} ++ ++static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val) ++{ ++ int ret; ++ ++ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum); ++ if (ret < 0) ++ return ret; ++ ++ ret = phy_write(phydev, REG_DEBUG_DATA, val); ++ ++ return ret; ++} ++ ++static int yt8010_config_aneg(struct phy_device *phydev) ++{ ++ phydev->speed = SPEED_100; ++ return 0; ++} ++ ++static int yt8512_clk_init(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL); ++ if (val < 0) ++ return val; ++ ++ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN; ++ ++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val); ++ if (ret < 0) ++ return ret; ++ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO); ++ if (val < 0) ++ return val; ++ ++ val |= YT8512_CONTROL1_RMII_EN; ++ ++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val); ++ if (ret < 0) ++ return ret; ++ ++ val = phy_read(phydev, MII_BMCR); ++ if (val < 0) ++ return val; ++ ++ val |= YT_SOFTWARE_RESET; ++ ret = phy_write(phydev, MII_BMCR, val); ++ ++ return ret; ++} ++ ++static int yt8512_led_init(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ int mask; ++ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0); ++ if (val < 0) ++ return val; ++ ++ val |= YT8512_LED0_ACT_BLK_IND; ++ ++ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN | ++ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN | ++ YT8512_LED0_BT_ON_EN; ++ val &= ~mask; ++ ++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val); ++ if (ret < 0) ++ return ret; ++ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1); ++ if (val < 0) ++ return val; ++ ++ val |= YT8512_LED1_BT_ON_EN; ++ ++ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN; ++ val &= ~mask; ++ ++ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val); ++ ++ return ret; ++} ++ ++static int yt8512_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ ++ ret = yt8512_clk_init(phydev); ++ if (ret < 0) ++ return ret; ++ ++ ret = yt8512_led_init(phydev); ++ ++ /* disable auto sleep */ ++ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1); ++ if (val < 0) ++ return val; ++ ++ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT)); ++ ++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val); ++ if (ret < 0) ++ return ret; ++ ++ return ret; ++} ++ ++static int yt8512_read_status(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ int speed, speed_mode, duplex; ++ ++ ret = genphy_update_link(phydev); ++ if (ret) ++ return ret; ++ ++ val = phy_read(phydev, REG_PHY_SPEC_STATUS); ++ if (val < 0) ++ return val; ++ ++ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT; ++ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT; ++ switch (speed_mode) { ++ case 0: ++ speed = SPEED_10; ++ break; ++ case 1: ++ speed = SPEED_100; ++ break; ++ case 2: ++ case 3: ++ default: ++ speed = SPEED_UNKNOWN; ++ break; ++ } ++ ++ phydev->speed = speed; ++ phydev->duplex = duplex; ++ ++ return 0; ++} ++ ++static int yt8521_config_init(struct phy_device *phydev) ++{ ++ int ret; ++ int val; ++ ++ /* disable auto sleep */ ++ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1); ++ if (val < 0) ++ return val; ++ ++ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT)); ++ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val); ++ if (ret < 0) ++ return ret; ++ ++ /* switch to access UTP */ ++ ret = ytphy_write_ext(phydev, 0xa000, 0); ++ if (ret < 0) ++ return ret; ++ ++ /* enable RXC clock when no wire plug */ ++ val = ytphy_read_ext(phydev, 0xc); ++ if (val < 0) ++ return val; ++ ++ val &= ~(1 << 12); ++ ret = ytphy_write_ext(phydev, 0xc, val); ++ if (ret < 0) ++ return ret; ++ ++ /* output SyncE clock (125mhz) even link is down */ ++ ret = ytphy_write_ext(phydev, 0xa012, 0x38); ++ if (ret < 0) ++ return ret; ++ ++ /* disable rgmii clk 2ns delay */ ++ val = ytphy_read_ext(phydev, 0xa001); ++ if (val < 0) ++ return val; ++ ++ val &= ~(1 << 8); ++ ret = ytphy_write_ext(phydev, 0xa001, val); ++ if (ret < 0) ++ return ret; ++ ++ /* setup delay */ ++ val = (1 << 10) | (0xf << 4) | 5; ++ ret = ytphy_write_ext(phydev, 0xa003, val); ++ if (ret < 0) ++ return ret; ++ ++ /* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */ ++ ytphy_write_ext(phydev, 0xa00b, 0xe004); ++ ytphy_write_ext(phydev, 0xa00c, 0); ++ ytphy_write_ext(phydev, 0xa00d, 0x2600); ++ ytphy_write_ext(phydev, 0xa00e, 0x0070); ++ ytphy_write_ext(phydev, 0xa00f, 0x000a); ++ ++ return 0; ++} ++ ++static int yt8521_ack_interrupt(struct phy_device *phydev) ++{ ++ int val; ++ ++ val = phy_read(phydev, REG_INT_STATUS); ++ phydev_dbg(phydev, "intr status 0x04%x\n", val); ++ ++ return (val < 0) ? val : 0; ++} ++ ++static int yt8521_config_intr(struct phy_device *phydev) ++{ ++ int val; ++ int err; ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) ++ val = BIT(14) | BIT(13) | BIT(11) | BIT(10); ++ else ++ val = 0; ++ ++ err = phy_write(phydev, REG_INT_MASK, val); ++ if (err) ++ return err; ++ err = yt8521_ack_interrupt(phydev); ++ ++ return err; ++} ++ ++static struct phy_driver ytphy_drvs[] = { ++ { ++ .phy_id = PHY_ID_YT8010, ++ .name = "YT8010 Automotive Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_BASIC_FEATURES, ++ .config_aneg = yt8010_config_aneg, ++ .read_status = genphy_read_status, ++ }, { ++ .phy_id = PHY_ID_YT8510, ++ .name = "YT8510 100/10Mb Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_BASIC_FEATURES, ++ .read_status = genphy_read_status, ++ }, { ++ .phy_id = PHY_ID_YT8511, ++ .name = "YT8511 Gigabit Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_GBIT_FEATURES, ++ .read_status = genphy_read_status, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, { ++ .phy_id = PHY_ID_YT8512, ++ .name = "YT8512 Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_BASIC_FEATURES, ++ .config_init = yt8512_config_init, ++ .read_status = yt8512_read_status, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, { ++ .phy_id = PHY_ID_YT8512B, ++ .name = "YT8512B Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ .features = PHY_BASIC_FEATURES, ++ .config_init = yt8512_config_init, ++ .read_status = yt8512_read_status, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, { ++ .phy_id = PHY_ID_YT8521, ++ .name = "YT8521 Ethernet", ++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK, ++ /* PHY_GBIT_FEATURES */ ++ .config_init = yt8521_config_init, ++ .config_intr = yt8521_config_intr, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ }, ++}; ++ ++module_phy_driver(ytphy_drvs); ++ ++MODULE_DESCRIPTION("Motorcomm PHY driver"); ++MODULE_AUTHOR("Leilei Zhao"); ++MODULE_LICENSE("GPL"); ++ ++static struct mdio_device_id __maybe_unused motorcomm_tbl[] = { ++ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK }, ++ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); +diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h +new file mode 100644 +index 000000000000..1e48c3671b69 +--- /dev/null ++++ b/include/linux/motorcomm_phy.h +@@ -0,0 +1,67 @@ ++/* ++ * include/linux/motorcomm_phy.h ++ * ++ * Motorcomm PHY IDs ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef _MOTORCOMM_PHY_H ++#define _MOTORCOMM_PHY_H ++ ++#define MOTORCOMM_PHY_ID_MASK 0x00000fff ++ ++#define PHY_ID_YT8010 0x00000309 ++#define PHY_ID_YT8510 0x00000109 ++#define PHY_ID_YT8511 0x0000010a ++#define PHY_ID_YT8512 0x00000118 ++#define PHY_ID_YT8512B 0x00000128 ++#define PHY_ID_YT8521 0x0000011a ++ ++#define REG_PHY_SPEC_STATUS 0x11 ++#define REG_INT_MASK 0x12 ++#define REG_INT_STATUS 0x13 ++#define REG_DEBUG_ADDR_OFFSET 0x1e ++#define REG_DEBUG_DATA 0x1f ++ ++#define YT8512_EXTREG_AFE_PLL 0x50 ++#define YT8512_EXTREG_EXTEND_COMBO 0x4000 ++#define YT8512_EXTREG_LED0 0x40c0 ++#define YT8512_EXTREG_LED1 0x40c3 ++ ++#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027 ++ ++#define YT_SOFTWARE_RESET 0x8000 ++ ++#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040 ++#define YT8512_CONTROL1_RMII_EN 0x0001 ++#define YT8512_LED0_ACT_BLK_IND 0x1000 ++#define YT8512_LED0_DIS_LED_AN_TRY 0x0001 ++#define YT8512_LED0_BT_BLK_EN 0x0002 ++#define YT8512_LED0_HT_BLK_EN 0x0004 ++#define YT8512_LED0_COL_BLK_EN 0x0008 ++#define YT8512_LED0_BT_ON_EN 0x0010 ++#define YT8512_LED1_BT_ON_EN 0x0010 ++#define YT8512_LED1_TXACT_BLK_EN 0x0100 ++#define YT8512_LED1_RXACT_BLK_EN 0x0200 ++#define YT8512_SPEED_MODE 0xc000 ++#define YT8512_DUPLEX 0x2000 ++ ++#define YT8512_SPEED_MODE_BIT 14 ++#define YT8512_DUPLEX_BIT 13 ++#define YT8512_EN_SLEEP_SW_BIT 15 ++ ++#define YT8521_EXTREG_SLEEP_CONTROL1 0x27 ++#define YT8521_EN_SLEEP_SW_BIT 15 ++ ++#define YT8521_SPEED_MODE 0xc000 ++#define YT8521_DUPLEX 0x2000 ++#define YT8521_SPEED_MODE_BIT 14 ++#define YT8521_DUPLEX_BIT 13 ++#define YT8521_LINK_STATUS_BIT 10 ++ ++#endif /* _MOTORCOMM_PHY_H */