fb7484f3f9
* update the defconfig and accomodate upstream changes * introduce hdmi/vop/phy drivers and enable hdmi * fix clock driver
31 lines
1.1 KiB
Diff
31 lines
1.1 KiB
Diff
From ac3f6f2e9cbe96d11a0db2801699669b2941cd09 Mon Sep 17 00:00:00 2001
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From: Paolo Sabatino <paolo.sabatino@gmail.com>
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Date: Mon, 29 Apr 2024 16:17:17 +0200
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Subject: [PATCH 1/4] fix borked DWC2 OTG driver
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---
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drivers/usb/gadget/dwc2_udc_otg_phy.c | 7 +------
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1 file changed, 1 insertion(+), 6 deletions(-)
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diff --git a/drivers/usb/gadget/dwc2_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c
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index 7f8e9564b9..e87f8b5e47 100644
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--- a/drivers/usb/gadget/dwc2_udc_otg_phy.c
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+++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c
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@@ -59,12 +59,7 @@ void otg_phy_init(struct dwc2_udc *dev)
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writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
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&~FORCE_SUSPEND_0), &phy->phypwr);
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- if (s5p_cpu_id == 0x4412)
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- writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
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- EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
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- &phy->phyclk); /* PLL 24Mhz */
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- else
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- writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
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+ writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
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CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
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writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
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--
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2.34.1
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