582 lines
13 KiB
Diff
582 lines
13 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Mateusz Koza <mateusz.koza@grinn-global.com>
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Date: Fri, 18 Jul 2025 14:49:59 +0200
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Subject: Add support for Grinn GenioSBC-700
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Add device tree support for the Grinn GenioSBC-700 single-board
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computer. This SBC is based on the Grinn GenioSOM-700 module, which
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integrates MediaTek's Genio 700 SoC.
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Hardware specifications and documentation can be found at:
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- https://grinn-global.com/products/grinn-geniosom-700
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- https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc
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---
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arch/arm/dts/Makefile | 3 +-
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arch/arm/dts/grinn-genio-700-sbc.dts | 24 +
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arch/arm/dts/grinn-genio-sbc.dtsi | 258 ++++++++++
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arch/arm/dts/grinn-genio-som.dtsi | 98 ++++
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configs/grinn_genio_700_sbc_defconfig | 140 +++++
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5 files changed, 522 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 111111111111..222222222222 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -1251,7 +1251,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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genio-1200-evk-ufs-qspi.dtb \
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genio-1200-radxa-nio-12l-d4.dtb \
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genio-1200-radxa-nio-12l-d8.dtb \
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- genio-1200-radxa-nio-12l-d16.dtb
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+ genio-1200-radxa-nio-12l-d16.dtb \
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+ grinn-genio-700-sbc.dtb
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dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb
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dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
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diff --git a/arch/arm/dts/grinn-genio-700-sbc.dts b/arch/arm/dts/grinn-genio-700-sbc.dts
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new file mode 100644
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index 000000000000..111111111111
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--- /dev/null
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+++ b/arch/arm/dts/grinn-genio-700-sbc.dts
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@@ -0,0 +1,24 @@
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+// SPDX-License-Identifier: GPL-2.0 OR MIT
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+/*
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+ * Copyright (C) 2025 Grinn sp. z o.o.
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+ * Author: Mateusz Koza <mateusz.koza@grinn-global.com>
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+ */
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+
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+/dts-v1/;
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+
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+#include <config.h>
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+
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+#include "mt8188.dtsi"
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+#include "mt6359.dtsi"
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+#include "grinn-genio-som.dtsi"
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+#include "grinn-genio-sbc.dtsi"
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+
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+/ {
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+ model = "Grinn GenioSBC-700";
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+ compatible = "grinn,genio-700-sbc", "mediatek,mt8188";
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+ memory@40000000 {
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+ /* 4GB */
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+ device_type = "memory";
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+ reg = <0 0x40000000 1 0x00000000>;
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+ };
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+};
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diff --git a/arch/arm/dts/grinn-genio-sbc.dtsi b/arch/arm/dts/grinn-genio-sbc.dtsi
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new file mode 100644
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index 000000000000..111111111111
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--- /dev/null
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+++ b/arch/arm/dts/grinn-genio-sbc.dtsi
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@@ -0,0 +1,258 @@
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+// SPDX-License-Identifier: GPL-2.0 OR MIT
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+/*
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+ * Copyright (C) 2025 Grinn sp. z o.o.
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+ * Author: Mateusz Koza <mateusz.koza@grinn-global.com>
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+ */
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+
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+/ {
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+ chosen {
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+ stdout-path = &uart0;
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+ };
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+
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+ usbhub_reset: usbhub-reset {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usbhub-reset";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ gpio = <&gpio 7 GPIO_ACTIVE_HIGH>;
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+ enable-active-low;
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+ };
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c0_pin>;
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+ clock-frequency = <400000>;
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+ status = "okay";
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+};
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+
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+&i2c2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c2_pin>;
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+ clock-frequency = <400000>;
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+ status = "okay";
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+};
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+
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+&i2c3 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c3_pin>;
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+ clock-frequency = <400000>;
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+ status = "okay";
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+};
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+
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+&i2c5 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c5_pin>;
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+ clock-frequency = <400000>;
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+ status = "okay";
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+};
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+
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+&i2c6 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c6_pin>;
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+ clock-frequency = <400000>;
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+ status = "okay";
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+};
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+
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+&pio {
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+ i2c0_pin: i2c0-pin {
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+ pins-bus {
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+ pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
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+ <PINMUX_GPIO55__FUNC_B1_SCL0>;
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+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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+ mediatek,drive-strength-adv = <7>;
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+ };
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+ };
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+
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+ i2c2_pin: i2c2-pin {
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+ pins-bus {
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+ pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
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+ <PINMUX_GPIO59__FUNC_B1_SCL2>;
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+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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+ mediatek,drive-strength-adv = <7>;
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+ };
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+ };
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+
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+ i2c3_pin: i2c3-pin {
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+ pins-bus {
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+ pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
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+ <PINMUX_GPIO61__FUNC_B1_SCL3>;
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+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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+ mediatek,drive-strength-adv = <7>;
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+ };
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+ };
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+
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+ i2c5_pin: i2c5-pin {
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+ pins-bus {
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+ pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
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+ <PINMUX_GPIO65__FUNC_B1_SCL5>;
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+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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+ mediatek,drive-strength-adv = <7>;
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+ };
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+ };
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+
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+ i2c6_pin: i2c6-pin {
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+ pins-bus {
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+ pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
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+ <PINMUX_GPIO67__FUNC_B1_SCL6>;
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+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
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+ mediatek,drive-strength-adv = <7>;
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+ };
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+ };
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+
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+ eth_default_pins: ethdefault {
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+ pins-cc {
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+ pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>,
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+ <PINMUX_GPIO140__FUNC_I0_GBE_RXC>,
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+ <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>,
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+ <PINMUX_GPIO142__FUNC_O_GBE_TXEN>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ };
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+
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+ pins-mdio {
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+ pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>,
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+ <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ input-enable;
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+ };
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+
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+ pins-power {
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+ pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>,
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+ <PINMUX_GPIO146__FUNC_B_GPIO146>;
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+ output-high;
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+ };
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+
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+ pins-rxd {
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+ pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>,
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+ <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>,
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+ <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>,
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+ <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ };
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+
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+ pins-txd {
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+ pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>,
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+ <PINMUX_GPIO132__FUNC_O_GBE_TXD2>,
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+ <PINMUX_GPIO133__FUNC_O_GBE_TXD1>,
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+ <PINMUX_GPIO134__FUNC_O_GBE_TXD0>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ };
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+ };
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+
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+ eth_sleep_pins: ethsleep {
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+ pins-cc {
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+ pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>,
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+ <PINMUX_GPIO140__FUNC_B_GPIO140>,
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+ <PINMUX_GPIO141__FUNC_B_GPIO141>,
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+ <PINMUX_GPIO142__FUNC_B_GPIO142>;
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+ };
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+
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+ pins-mdio {
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+ pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>,
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+ <PINMUX_GPIO144__FUNC_B_GPIO144>;
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+ input-disable;
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+ bias-disable;
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+ };
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+
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+ pins-rxd {
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+ pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>,
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+ <PINMUX_GPIO136__FUNC_B_GPIO136>,
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+ <PINMUX_GPIO137__FUNC_B_GPIO137>,
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+ <PINMUX_GPIO138__FUNC_B_GPIO138>;
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+ };
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+
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+ pins-txd {
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+ pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>,
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+ <PINMUX_GPIO132__FUNC_B_GPIO132>,
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+ <PINMUX_GPIO133__FUNC_B_GPIO133>,
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+ <PINMUX_GPIO134__FUNC_B_GPIO134>;
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+ };
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+ };
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+};
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+
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+ð {
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+ phy-mode ="rgmii-rxid";
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+ phy-handle = <ðernet_phy0>;
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+ mediatek,tx-delay-ps = <2030>;
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+ pinctrl-names = "default", "sleep";
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+ pinctrl-0 = <ð_default_pins>;
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+ pinctrl-1 = <ð_sleep_pins>;
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+ snps,reset-active-low;
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+ snps,reset-delays-us = <0 11000 200000>;
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+ snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+
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+ mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ ethernet_phy0: ethphy0@3 {
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+ reg = <3>;
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ eee-broken-1000t;
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+ interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>;
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+ };
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+ };
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+};
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+
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+&watchdog {
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+ status = "okay";
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+};
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+
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+&auxadc {
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+ status = "okay";
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+};
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+
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+&u3phy0 {
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+ status = "okay";
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+};
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+
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+&u3phy1 {
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+ status = "okay";
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+};
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+
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+&u3phy2 {
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+ status = "okay";
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+};
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+
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+&u2port0 {
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+ status = "okay";
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+};
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+
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+&u2port1 {
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+ status = "okay";
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+};
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+
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+&u3port1 {
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+ status = "okay";
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+};
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+
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+&u2port2 {
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+ status = "okay";
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+};
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+
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+&usb {
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+ status = "okay";
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+};
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+
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+&ssusb {
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+ mediatek,force-vbus;
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+ maximum-speed = "high-speed";
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+ dr_mode = "peripheral";
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+ status = "okay";
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+};
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+
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+&xhci1 {
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+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
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+ vbus-supply = <&usbhub_reset>;
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+ status = "okay";
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+};
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+
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+&xhci2 {
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+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
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+ status = "okay";
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+};
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diff --git a/arch/arm/dts/grinn-genio-som.dtsi b/arch/arm/dts/grinn-genio-som.dtsi
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new file mode 100644
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index 000000000000..111111111111
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--- /dev/null
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+++ b/arch/arm/dts/grinn-genio-som.dtsi
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@@ -0,0 +1,98 @@
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+// SPDX-License-Identifier: GPL-2.0 OR MIT
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+/*
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+ * Copyright (C) 2025 Grinn sp. z o.o.
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+ * Author: Mateusz Koza <mateusz.koza@grinn-global.com>
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+ */
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+
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+/ {
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+ firmware: firmware {
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+ optee {
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+ compatible = "linaro,optee-tz";
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+ method = "smc";
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+ };
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+
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+ psci: psci {
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+ compatible = "arm,psci-1.0";
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+ method = "smc";
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+ };
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+ };
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+
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
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+ bl31_secmon_reserved: secmon@54600000 {
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+ no-map;
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+ reg = <0 0x54600000 0x0 0x200000>;
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+ };
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+
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+ /* 12 MiB reserved for OP-TEE (BL32)
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+ * +-----------------------+ 0x43e0_0000
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+ * | SHMEM 2MiB |
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+ * +-----------------------+ 0x43c0_0000
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+ * | | TA_RAM 8MiB |
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|
+ * + TZDRAM +--------------+ 0x4340_0000
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+ * | | TEE_RAM 2MiB |
|
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+ * +-----------------------+ 0x4320_0000
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+ */
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+ optee_reserved: optee@43200000 {
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+ no-map;
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+ reg = <0 0x43200000 0 0x00c00000>;
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+ };
|
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+ };
|
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+};
|
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+
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+&mt6359_vufs_ldo_reg {
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+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
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+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+};
|
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+
|
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+&mt6359_vemc_1_ldo_reg {
|
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+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
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+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+};
|
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+
|
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+&mt6359_vusb_ldo_reg {
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ bus-width = <8>;
|
|
+ max-frequency = <200000000>;
|
|
+ cap-mmc-highspeed;
|
|
+ mmc-hs200-1_8v;
|
|
+ mmc-hs400-1_8v;
|
|
+ hs400-ds-delay = <0x1481b>;
|
|
+ cap-mmc-hw-reset;
|
|
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
|
|
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
|
|
+ non-removable;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pin>;
|
|
+ clock-frequency = <400000>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
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+&pio {
|
|
+ i2c1_pin: i2c1-pin {
|
|
+ pins-bus {
|
|
+ pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
|
|
+ <PINMUX_GPIO57__FUNC_B1_SCL1>;
|
|
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
|
|
+ mediatek,drive-strength-adv = <7>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/configs/grinn_genio_700_sbc_defconfig b/configs/grinn_genio_700_sbc_defconfig
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|
new file mode 100644
|
|
index 000000000000..111111111111
|
|
--- /dev/null
|
|
+++ b/configs/grinn_genio_700_sbc_defconfig
|
|
@@ -0,0 +1,140 @@
|
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+CONFIG_ARM=y
|
|
+CONFIG_SYS_BOARD="genio-700-evk"
|
|
+CONFIG_COUNTER_FREQUENCY=13000000
|
|
+CONFIG_POSITION_INDEPENDENT=y
|
|
+CONFIG_ARCH_MEDIATEK=y
|
|
+CONFIG_SYS_TEXT_BASE=0x4c000000
|
|
+CONFIG_SYS_MALLOC_LEN=0x500000
|
|
+CONFIG_SYS_MALLOC_F_LEN=0x4000
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_ENV_SIZE=0x1000
|
|
+CONFIG_ENV_OFFSET=0x0
|
|
+CONFIG_DM_GPIO=y
|
|
+CONFIG_DEFAULT_DEVICE_TREE="grinn-genio-700-sbc"
|
|
+CONFIG_TARGET_MT8188=y
|
|
+CONFIG_DEBUG_UART_BASE=0x11001100
|
|
+CONFIG_DEBUG_UART_CLOCK=26000000
|
|
+CONFIG_ARMV8_CRYPTO=y
|
|
+CONFIG_SYS_LOAD_ADDR=0x4c000000
|
|
+CONFIG_DEBUG_UART=y
|
|
+CONFIG_DISTRO_DEFAULTS=y
|
|
+CONFIG_FIT=y
|
|
+CONFIG_FIT_SIGNATURE=y
|
|
+CONFIG_LEGACY_IMAGE_FORMAT=y
|
|
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
|
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt8390-grinn-genio-700-sbc"
|
|
+# CONFIG_DISPLAY_BOARDINFO is not set
|
|
+CONFIG_BOARD_LATE_INIT=y
|
|
+# CONFIG_CMD_CONSOLE is not set
|
|
+# CONFIG_CMD_BOOTD is not set
|
|
+CONFIG_SYS_BOOTM_LEN=0x5000000
|
|
+CONFIG_CMD_BOOTEFI_SELFTEST=y
|
|
+# CONFIG_CMD_ELF is not set
|
|
+# CONFIG_CMD_GO is not set
|
|
+# CONFIG_CMD_IMI is not set
|
|
+# CONFIG_CMD_XIMG is not set
|
|
+CONFIG_CMD_NVEDIT_EFI=y
|
|
+CONFIG_CMD_NVEDIT_INFO=y
|
|
+# CONFIG_CMD_CRC32 is not set
|
|
+CONFIG_CMD_ADC=y
|
|
+CONFIG_CMD_BIND=y
|
|
+CONFIG_CMD_CLK=y
|
|
+CONFIG_CMD_DFU=y
|
|
+CONFIG_CMD_DM=y
|
|
+CONFIG_CMD_GPIO=y
|
|
+CONFIG_CMD_GPT=y
|
|
+CONFIG_CMD_GPT_RENAME=y
|
|
+CONFIG_CMD_I2C=y
|
|
+# CONFIG_CMD_LOADB is not set
|
|
+# CONFIG_CMD_LOADS is not set
|
|
+CONFIG_CMD_MBR=y
|
|
+CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_USB=y
|
|
+CONFIG_CMD_USB_MASS_STORAGE=y
|
|
+# CONFIG_CMD_ITEST is not set
|
|
+CONFIG_CMD_BMP=y
|
|
+# CONFIG_CMD_BLOCK_CACHE is not set
|
|
+CONFIG_CMD_EFIDEBUG=y
|
|
+CONFIG_PARTITION_TYPE_GUID=y
|
|
+CONFIG_ENV_IS_IN_MMC=y
|
|
+CONFIG_SYS_MMC_ENV_PART=2
|
|
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
+CONFIG_ENV_IMPORT_FDT=y
|
|
+CONFIG_REGMAP=y
|
|
+CONFIG_SYSCON=y
|
|
+CONFIG_DEVRES=y
|
|
+CONFIG_ADC_MTK=y
|
|
+CONFIG_CLK=y
|
|
+CONFIG_DFU_MMC=y
|
|
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
|
|
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000
|
|
+CONFIG_USB_FUNCTION_FASTBOOT=y
|
|
+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000
|
|
+CONFIG_FASTBOOT_BUF_SIZE=0x8000000
|
|
+CONFIG_FASTBOOT_FLASH=y
|
|
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
|
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
|
|
+CONFIG_DM_I2C=y
|
|
+CONFIG_SYS_I2C_MTK=y
|
|
+# CONFIG_INPUT is not set
|
|
+CONFIG_MISC=y
|
|
+# CONFIG_MMC_QUIRKS is not set
|
|
+CONFIG_MMC_HS400_SUPPORT=y
|
|
+CONFIG_MMC_MTK=y
|
|
+CONFIG_PHY_REALTEK=y
|
|
+CONFIG_PHY_ETHERNET_ID=y
|
|
+CONFIG_DWC_ETH_QOS=y
|
|
+CONFIG_DWC_ETH_QOS_MTK=y
|
|
+CONFIG_PHY=y
|
|
+CONFIG_PHY_MTK_TPHY=y
|
|
+CONFIG_PINCTRL=y
|
|
+CONFIG_PINCONF=y
|
|
+CONFIG_PINCTRL_MT8188=y
|
|
+CONFIG_POWER_DOMAIN=y
|
|
+CONFIG_MTK_POWER_DOMAIN=y
|
|
+CONFIG_CMD_PMIC=y
|
|
+CONFIG_DM_PMIC=y
|
|
+CONFIG_MTK_PMIC_WRAP=y
|
|
+CONFIG_CMD_REGULATOR=y
|
|
+CONFIG_DM_REGULATOR=y
|
|
+CONFIG_DM_REGULATOR_FIXED=y
|
|
+CONFIG_DM_REGULATOR_MT6359=y
|
|
+CONFIG_DM_RTC=y
|
|
+CONFIG_RTC_EMULATION=y
|
|
+CONFIG_BAUDRATE=921600
|
|
+CONFIG_DM_SERIAL=y
|
|
+CONFIG_DEBUG_UART_ANNOUNCE=y
|
|
+CONFIG_MTK_SERIAL=y
|
|
+CONFIG_SYSRESET=y
|
|
+CONFIG_SYSRESET_PSCI=y
|
|
+CONFIG_USB=y
|
|
+CONFIG_DM_USB_GADGET=y
|
|
+CONFIG_USB_XHCI_HCD=y
|
|
+CONFIG_USB_XHCI_MTK=y
|
|
+CONFIG_USB_MTU3=y
|
|
+CONFIG_USB_KEYBOARD=y
|
|
+CONFIG_USB_GADGET=y
|
|
+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d
|
|
+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
|
|
+CONFIG_USB_ETHER=y
|
|
+CONFIG_DM_VIDEO=y
|
|
+CONFIG_VIDEO_MEDIATEK=y
|
|
+CONFIG_SPLASH_SCREEN=y
|
|
+CONFIG_SPLASH_SCREEN_ALIGN=y
|
|
+CONFIG_SPLASH_SOURCE=y
|
|
+CONFIG_BMP_24BPP=y
|
|
+CONFIG_WDT=y
|
|
+CONFIG_ERRNO_STR=y
|
|
+CONFIG_OF_LIBFDT_OVERLAY=y
|
|
+CONFIG_EFI_SET_TIME=y
|
|
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
|
|
+CONFIG_EFI_CAPSULE_ON_DISK=y
|
|
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
|
|
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
|
|
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
|
|
+CONFIG_LMB_MAX_REGIONS=16
|
|
+CONFIG_SYSINFO=y
|
|
+# CONFIG_SYSINFO_GAZERBEAM is not set
|
|
+# CONFIG_SYSINFO_SANDBOX is not set
|
|
+CONFIG_SYSINFO_SMBIOS=y
|
|
+# CONFIG_SYSINFO_GPIO is not set
|
|
--
|
|
Armbian
|
|
|