ecd55f4ba5
Mainline TF-A doesn't initialize SGRF_SOC_CON8-CON15 which control DMAC0 and DMAC1 configuration. Without this, the PL330 DMA controllers cannot be accessed from Linux and PERIPH_ID reads as 0x0. The fix configures SGRF registers to set DMAC manager threads to running state and non-secure mode, then pulses DMAC reset to apply the new configuration. Based on community reverse-engineering: - https://lists.denx.de/pipermail/u-boot/2023-April/514267.html - https://gist.github.com/CrystalGamma/a68333fa4c9fda7eb6c09d30ad4937fe Tested on Helios64 (RK3399). Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
95 lines
3.6 KiB
Diff
95 lines
3.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Armbian <info@armbian.com>
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Date: Thu, 23 Jan 2026 12:00:00 +0000
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Subject: [PATCH] rk3399: Initialize DMAC SGRF registers and reset for PL330 DMA
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Mainline TF-A doesn't initialize SGRF_SOC_CON8-CON15 which control
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DMAC0 and DMAC1 configuration. Without this, the PL330 DMA controllers
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cannot be accessed from Linux and PERIPH_ID reads as 0x0.
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Additionally, the SGRF configuration defines the manager thread state
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after reset, so we must pulse the DMAC reset for the new settings to
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take effect.
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Based on community reverse-engineering of RK3399 SGRF registers:
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- CON8[2]: DMAC0 manager thread state after reset (1=running)
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- CON8[3]: DMAC0 manager thread security state (1=non-secure)
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- CON8[4:15]: DMAC0 event/IRQ security state (1=non-secure)
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- CON9[0:11]: DMAC0 peripheral security state (1=non-secure)
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- Similar for DMAC1 in CON11-CON15
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Signed-off-by: Armbian <info@armbian.com>
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---
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plat/rockchip/rk3399/drivers/secure/secure.c | 33 ++++++++++++++++++++
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plat/rockchip/rk3399/drivers/secure/secure.h | 10 ++++++
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2 files changed, 43 insertions(+)
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diff --git a/plat/rockchip/rk3399/drivers/secure/secure.c b/plat/rockchip/rk3399/drivers/secure/secure.c
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index 13c83ca1f..b195fe940 100644
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--- a/plat/rockchip/rk3399/drivers/secure/secure.c
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+++ b/plat/rockchip/rk3399/drivers/secure/secure.c
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@@ -158,6 +158,39 @@ void secure_sgrf_init(void)
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SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
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SGRF_SLV_S_WMSK | SGRF_INTSRAM_S);
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+
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+ /*
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+ * Configure DMAC0 and DMAC1 SGRF registers.
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+ * Without this configuration, PL330 DMA controllers cannot be
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+ * accessed from Linux and PERIPH_ID reads as 0x0.
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+ */
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+ /* DMAC0: manager running, non-secure, all events/IRQs non-secure */
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+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8),
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+ REG_SOC_WMSK | SGRF_DMAC_CFG_NS);
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+ /* DMAC0: all peripherals non-secure */
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+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(9),
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+ REG_SOC_WMSK | SGRF_DMAC_PERIPH_NS);
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+
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+ /* DMAC1: manager running, non-secure, all events/IRQs non-secure */
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+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(11),
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+ REG_SOC_WMSK | SGRF_DMAC_CFG_NS);
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+ /* DMAC1: all peripherals non-secure */
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+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(12),
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+ REG_SOC_WMSK | SGRF_DMAC_PERIPH_NS);
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+
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+ /*
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+ * Reset DMAC0 and DMAC1 to apply new SGRF configuration.
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+ * The SGRF configuration defines the state after reset, so we
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+ * must pulse the reset for the new settings to take effect.
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+ */
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+ /* Assert DMAC0 and DMAC1 reset */
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+ mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
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+ CRU_DMAC0_RST | CRU_DMAC1_RST);
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+ /* Small delay to ensure reset is recognized */
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+ udelay(1);
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+ /* Deassert DMAC0 and DMAC1 reset */
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+ mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
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+ CRU_DMAC0_RST_RLS | CRU_DMAC1_RST_RLS);
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}
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void secure_sgrf_ddr_rgn_init(void)
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diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h
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index 79997b2f6..91c4b2a30 100644
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--- a/plat/rockchip/rk3399/drivers/secure/secure.h
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+++ b/plat/rockchip/rk3399/drivers/secure/secure.h
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@@ -40,6 +40,16 @@
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#define SGRF_INTSRAM_S BIT(13)
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+/*
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+ * DMAC SGRF configuration:
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+ * - bit[2]: manager thread state after reset (1=running, 0=halt)
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+ * - bit[3]: manager thread security state (1=non-secure)
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+ * - bit[4:15]: event/IRQ security state bits (1=non-secure)
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+ * Set all to non-secure and running.
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+ */
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+#define SGRF_DMAC_CFG_NS (0xFFFC) /* bits 2-15 set */
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+#define SGRF_DMAC_PERIPH_NS (0x0FFF) /* peripheral security bits */
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+
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/* ddr region */
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#define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */
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--
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2.39.0
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