1a12994e79
* [Early WIP] Update sunxi-next to kernel 4.17 * Switch Allwinner 32 and 64bit to U-boot 2018.05 * Adjust patched for 4.17.y / sunxi-next - adjust both configurations - removing FAT support from u-boot (breaks if you try to save) Tested those boards: Cubietruck: wlan fails http://ix.io/1fYS USB OK, HDMI yes Bananapi R40: http://ix.io/1fZm USB OK, HDMI yes Lime A64: USB no, HDMI no, wireless buggy, eMMC yes Orangepi prime H5: OK http://ix.io/1fZJ DVFS no Orangepi2e: DVFS OK, HDMI OK, net OK, wifi OK, eMMC ok, http://ix.io/1fZT * Kernel config update, enabling HDMI on CT+ * Trying to fix A64 HDMI but failed. Fixed M64 ethernet instead * Update orangepioneplus.wip * Update orangepioneplus.wip * Fix H6 build process * Add regulator bits for Orangepizero+, thanks to @5kft * add H5 support for optional 1.3v regulator and 1.3GHz operation This patch adds two optional overlays that can be used to: 1) enable the 1.1v/1.3v regulator on boards that provide the necessary compatible H/W support 2) modify the default CPU clock operating table to add new 1.2GHz and 1.3GHz clocks Note that the generated regulator overlay will only support boards whose 1.1v/1.3v regulator is controlled by GPIO PL6. * updates for the NanoPi NEO Plus2 This change introduces a patch that provides two changes for the NanoPi NEO Plus2: * Configure the "cpu0" to use the "vdd_cpux" regulator; this enables the ability to use higher CPU clocks * Correct the configurations of the on-board power and status LEDs * Adjust nightly building and few boards config cleanup
62 lines
1.4 KiB
Diff
62 lines
1.4 KiB
Diff
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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index 422589b3..58821018 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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@@ -48,11 +48,17 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- cpu@0 {
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+ cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0>;
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+ clocks = <&ccu CLK_CPUX>;
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+ clock-names = "cpu";
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+ clock-latency = <244144>; /* 8 32k periods */
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enable-method = "psci";
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+ operating-points-v2 = <&cpu_opp_table>;
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+ cpu-supply = <®_cpu_fallback>;
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+ #cooling-cells = <2>;
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};
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cpu@1 {
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@@ -60,6 +65,7 @@
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@2 {
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@@ -67,6 +73,7 @@
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@3 {
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@@ -74,6 +81,7 @@
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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};
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@@ -173,6 +181,13 @@
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};
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};
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+ reg_cpu_fallback: reg_cpu_fallback {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd-cpux-dummy";
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+ regulator-min-microvolt = <1100000>;
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+ regulator-max-microvolt = <1100000>;
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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