a57ce78b37
* Bump to 4.18, removing the obvious, fixing build problems, put some on waiting. * Pin 4.18 to DEV, rollback 4.14 to NEXT, adjust configs, remove one deprecated patch from NEXT and add board-h3-address-some-stability-issues.patch * Adjust few boards in development to new reality, removing it from NEXT for now * Adjust few board configs * Board config adjustement * Adjust few boards configs * Port NeoCore2 and Neo21.1 to 4.14.y * Adjust board config * Adjust board config
29 lines
1.0 KiB
Diff
29 lines
1.0 KiB
Diff
The GPU clock on H3 has only one parent, PLL-GPU, and the PLL is only
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the parent of the GPU clock. The GPU clock can be tweaked by tweaking
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the PLL-GPU clock.
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Add CLK_SET_RATE_PARENT flag to allow tweaking the GPU clock via
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tweaking PLL-GPU.
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Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
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Signed-off-by: Icenowy Zheng <icenowy at aosc.io>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 7a81c4885836..543c46d0e045 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -484,7 +484,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
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0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
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static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
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- 0x1a0, 0, 3, BIT(31), 0);
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+ 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
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static struct ccu_common *sun8i_h3_ccu_clks[] = {
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&pll_cpux_clk.common,
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--
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2.13.5
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