9e29827ad9
- `risc-v`: rework RichNeese's boards, reduce families, move tweaks to boards - `risc-v`/`starfive`: `CONFIG_MOTORCOMM_PHY=m` for the onboard Ethernet - `risc-v`/`starfive`: use mainline kernel 6.1.y, with StarFive's rebased patches against `v6.1.5` - from https://github.com/starfive-tech/linux/commits/visionfive - contention point: `1022-soc-sifive-ccache-Add-StarFive-JH71x0-support.patch` which I merged half-assed, need review/fixes? - `risc-v`/`starfive`: update kernel config, sans changes - `risc-v`/`starfive`: switch from `grub` to `extlinux` - `risc-v`/`starfive`: new `starfive` family with their (vendor) kernel Co-authored-by: Richard Neese <r.neese@gmail.com>
30 lines
914 B
Diff
30 lines
914 B
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Tue, 27 Apr 2021 17:05:57 +0200
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Subject: spi: cadence-quadspi: Allow compilation on RISC-V
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This IP is also used on the StarFive JH7100 riscv64 SoC and presumably
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also the upcoming JH7110 SoC.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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drivers/spi/Kconfig | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
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index d1bb62f7368b..02d35670598e 100644
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -230,7 +230,7 @@ config SPI_CADENCE
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config SPI_CADENCE_QUADSPI
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tristate "Cadence Quad SPI controller"
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- depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
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+ depends on OF && (ARM || ARM64 || RISCV || X86 || COMPILE_TEST)
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help
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Enable support for the Cadence Quad SPI Flash controller.
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--
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Armbian
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