1a12994e79
* [Early WIP] Update sunxi-next to kernel 4.17 * Switch Allwinner 32 and 64bit to U-boot 2018.05 * Adjust patched for 4.17.y / sunxi-next - adjust both configurations - removing FAT support from u-boot (breaks if you try to save) Tested those boards: Cubietruck: wlan fails http://ix.io/1fYS USB OK, HDMI yes Bananapi R40: http://ix.io/1fZm USB OK, HDMI yes Lime A64: USB no, HDMI no, wireless buggy, eMMC yes Orangepi prime H5: OK http://ix.io/1fZJ DVFS no Orangepi2e: DVFS OK, HDMI OK, net OK, wifi OK, eMMC ok, http://ix.io/1fZT * Kernel config update, enabling HDMI on CT+ * Trying to fix A64 HDMI but failed. Fixed M64 ethernet instead * Update orangepioneplus.wip * Update orangepioneplus.wip * Fix H6 build process * Add regulator bits for Orangepizero+, thanks to @5kft * add H5 support for optional 1.3v regulator and 1.3GHz operation This patch adds two optional overlays that can be used to: 1) enable the 1.1v/1.3v regulator on boards that provide the necessary compatible H/W support 2) modify the default CPU clock operating table to add new 1.2GHz and 1.3GHz clocks Note that the generated regulator overlay will only support boards whose 1.1v/1.3v regulator is controlled by GPIO PL6. * updates for the NanoPi NEO Plus2 This change introduces a patch that provides two changes for the NanoPi NEO Plus2: * Configure the "cpu0" to use the "vdd_cpux" regulator; this enables the ability to use higher CPU clocks * Correct the configurations of the on-board power and status LEDs * Adjust nightly building and few boards config cleanup
90 lines
3.9 KiB
Diff
90 lines
3.9 KiB
Diff
From c19926638d14b39bba73461f7e4750fb1926d03e Mon Sep 17 00:00:00 2001
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From: Marcus Cooper <codekipper@gmail.com>
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Date: Tue, 5 Sep 2017 09:50:31 +0200
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Subject: [PATCH] ASoC: sun4i-i2s: Add regmap field to sign extend sample
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On the newer SoCs this is set by default to transfer a 0 after
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each sample in each slot. Add the regmap field to configure this
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and set it so that it pads the sample with 0s.
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Signed-off-by: Marcus Cooper <codekipper@gmail.com>
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---
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sound/soc/sunxi/sun4i-i2s.c | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
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index 04f92583a9696..7826fb3523c1b 100644
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--- a/sound/soc/sunxi/sun4i-i2s.c
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+++ b/sound/soc/sunxi/sun4i-i2s.c
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@@ -138,6 +138,7 @@
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* @field_fmt_bclk: regmap field to set clk polarity.
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* @field_fmt_lrclk: regmap field to set frame polarity.
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* @field_fmt_mode: regmap field to set the operational mode.
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+ * @field_fmt_sext: regmap field to set the sign extension.
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* @field_txchanmap: location of the tx channel mapping register.
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* @field_rxchanmap: location of the rx channel mapping register.
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* @field_txchansel: location of the tx channel select bit fields.
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@@ -163,6 +164,7 @@ struct sun4i_i2s_quirks {
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struct reg_field field_fmt_bclk;
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struct reg_field field_fmt_lrclk;
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struct reg_field field_fmt_mode;
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+ struct reg_field field_fmt_sext;
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struct reg_field field_txchanmap;
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struct reg_field field_rxchanmap;
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struct reg_field field_txchansel;
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@@ -187,6 +189,7 @@ struct sun4i_i2s {
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struct regmap_field *field_fmt_bclk;
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struct regmap_field *field_fmt_lrclk;
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struct regmap_field *field_fmt_mode;
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+ struct regmap_field *field_fmt_sext;
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struct regmap_field *field_txchanmap;
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struct regmap_field *field_rxchanmap;
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struct regmap_field *field_txchansel;
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@@ -337,6 +340,9 @@ static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s,
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SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
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SUN8I_I2S_FMT0_LRCK_PERIOD(32));
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+ /* Set sign extension to pad out LSB with 0 */
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+ regmap_field_write(i2s->field_fmt_sext, 0);
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+
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return 0;
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}
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@@ -874,6 +880,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
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.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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.has_slave_select_bit = true,
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.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
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+ .field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
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.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
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.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
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.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
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@@ -891,6 +898,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
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.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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.has_slave_select_bit = true,
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.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
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+ .field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
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.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
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.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
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.field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
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@@ -914,6 +922,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
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.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
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.field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
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+ .field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 4, 5),
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.field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
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.field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
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.field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
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@@ -959,6 +968,12 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
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if (IS_ERR(i2s->field_fmt_mode))
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return PTR_ERR(i2s->field_fmt_mode);
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+ i2s->field_fmt_sext =
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+ devm_regmap_field_alloc(dev, i2s->regmap,
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+ i2s->variant->field_fmt_sext);
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+ if (IS_ERR(i2s->field_fmt_sext))
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+ return PTR_ERR(i2s->field_fmt_sext);
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+
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i2s->field_txchanmap =
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devm_regmap_field_alloc(dev, i2s->regmap,
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i2s->variant->field_txchanmap);
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