54bc65b3bb
* Bump rockchip DEV 32b to 5.11.y * Move mvebu64 DEV to 5.11.y * Move Rockchip64 DEV to 5.11.y Disabling general-rkvdec_nv15.patch - need more attention * Add Meson DEV / Odroid C1 * Move OdroidXU4 DEV to tobetter's 5.11.y branch * Bump sunxi DEV to 5.11.y * Bump mvebu DEV to 5.11.y
47 lines
1.6 KiB
Diff
47 lines
1.6 KiB
Diff
From 435bdc2bdfd2bd37e96b42c7c972ce271e06d90c Mon Sep 17 00:00:00 2001
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From: Douglas Anderson <dianders@chromium.org>
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Date: Mon, 11 Jul 2016 19:05:36 +0800
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Subject: [PATCH 06/14] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always
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Jitter was improved by lowering the MPLL bandwidth to account for high
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frequency noise in the rk3288 PLL. In each case MPLL bandwidth was
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lowered only enough to get us a comfortable margin. We believe that
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lowering the bandwidth like this is safe given sufficient testing.
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Signed-off-by: Douglas Anderson <dianders@chromium.org>
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Signed-off-by: Yakir Yang <ykk@rock-chips.com>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++--------------
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1 file changed, 2 insertions(+), 14 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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index 7f56d8c34..7d7ee5b26 100644
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -159,20 +159,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
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static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{
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- 40000000, { 0x0018, 0x0018, 0x0018 },
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- }, {
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- 65000000, { 0x0028, 0x0028, 0x0028 },
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- }, {
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- 66000000, { 0x0038, 0x0038, 0x0038 },
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- }, {
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- 74250000, { 0x0028, 0x0038, 0x0038 },
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- }, {
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- 83500000, { 0x0028, 0x0038, 0x0038 },
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- }, {
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- 146250000, { 0x0038, 0x0038, 0x0038 },
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- }, {
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- 148500000, { 0x0000, 0x0038, 0x0038 },
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- }, {
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+ 600000000, { 0x0000, 0x0000, 0x0000 },
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+ }, {
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~0UL, { 0x0000, 0x0000, 0x0000},
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}
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};
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--
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2.26.2
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