2e5611c92d
Re-extract the kernel patches as a series. Re-extract the u-boot patches as "git format-patch" command. Unified patch extraction makes it easier to work with patches.
555 lines
18 KiB
Diff
555 lines
18 KiB
Diff
From 1600b3620dd8babffcfcc7d780a31723c94270bc Mon Sep 17 00:00:00 2001
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From: James Deng <james.deng@spacemit.com>
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Date: Thu, 1 Aug 2024 22:09:26 +0800
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Subject: Update for v1.0.11
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---
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debian/control | 1 +
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debian/rules | 10 ++
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include/sbi_utils/cache/cacheflush.h | 29 ++++
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lib/utils/psci/psci_main.c | 8 +-
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.../spacemit/plat/k1x/underly_implement.c | 86 +++++++++++-
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lib/utils/psci/spacemit/plat/plat_pm.c | 131 ++++++++++++++----
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.../psci/spacemit/plat/underly_implement.h | 2 +
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lib/utils/serial/fdt_serial_uart8250.c | 1 +
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.../generic/include/spacemit/k1x/k1x_evb.h | 1 +
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platform/generic/spacemit/spacemit_k1.c | 23 +--
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10 files changed, 246 insertions(+), 46 deletions(-)
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diff --git a/debian/control b/debian/control
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index 6c4a1747b5f3..f0f186707ea7 100644
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--- a/debian/control
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+++ b/debian/control
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@@ -11,6 +11,7 @@ Rules-Requires-Root: no
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Vcs-Browser: https://salsa.debian.org/opensbi-team/opensbi
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Vcs-Git: https://salsa.debian.org/opensbi-team/opensbi.git
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Homepage: https://github.com/riscv-software-src/opensbi
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+XBS-Commit-Id:
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Package: opensbi-spacemit
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Architecture: all
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diff --git a/debian/rules b/debian/rules
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index ab9cc10c406c..3d44b43fcc38 100755
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--- a/debian/rules
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+++ b/debian/rules
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@@ -10,9 +10,19 @@ else
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VERBOSE=0
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endif
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+# 检查是否在 Git 仓库中，并获取 commit ID
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+GIT_INSIDE := $(shell git rev-parse --is-inside-work-tree 2>/dev/null)
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+ifeq ($(GIT_INSIDE),true)
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+ COMMIT_ID := $(shell git rev-parse --short HEAD)
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+endif
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+
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%:
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dh $@
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+override_dh_auto_configure:
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+ sed -i "s/XBS-Commit-Id:.*/XBS-Commit-Id: $(COMMIT_ID)/" debian/control
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+ dh_auto_configure
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+
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override_dh_auto_build:
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make \
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V=$(VERBOSE) \
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diff --git a/include/sbi_utils/cache/cacheflush.h b/include/sbi_utils/cache/cacheflush.h
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index 126931b25888..7887eef949ab 100644
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--- a/include/sbi_utils/cache/cacheflush.h
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+++ b/include/sbi_utils/cache/cacheflush.h
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@@ -197,4 +197,33 @@ static inline void csi_flush_l2_cache(bool hw)
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writel((1 << L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET) | (1 << L2_CACHE_FLUSH_HW_EN_BIT_OFFSET), cr);
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}
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}
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+
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+static inline void csi_flush_l2_cache_hart(bool hw, int hartid)
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+{
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+ uintptr_t *cr =(MPIDR_AFFLVL1_VAL(hartid) == 0) ? (uintptr_t *)CLUSTER0_L2_CACHE_FLUSH_REG_BASE :
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+ (uintptr_t *)CLUSTER1_L2_CACHE_FLUSH_REG_BASE;
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+
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+ if (!hw) {
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+ writel(0x0, cr);
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+ /* flush l2 cache */
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+ writel(readl(cr) | (1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
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+ /* k1pro */
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+ if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
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+ while (readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET));
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+ else /* k1x */ {
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+ /* clear the request */
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+ while (1) {
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+ if ((readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET)) == 0)
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+ break;
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+ __mdelay();
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+ }
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+ writel(readl(cr) & ~(1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
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+ }
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+ } else {
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+ /* k1pro */
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+ if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
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+ return /* do nothing */;
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+ writel((1 << L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET) | (1 << L2_CACHE_FLUSH_HW_EN_BIT_OFFSET), cr);
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+ }
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+}
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#endif
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diff --git a/lib/utils/psci/psci_main.c b/lib/utils/psci/psci_main.c
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index a3ce138c00cc..e89bb4ad3f39 100644
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--- a/lib/utils/psci/psci_main.c
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+++ b/lib/utils/psci/psci_main.c
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@@ -81,10 +81,10 @@ int psci_cpu_off(void)
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* The only error cpu_off can return is E_DENIED. So check if that's
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* indeed the case.
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*/
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- if (rc != PSCI_E_DENIED) {
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- sbi_printf("%s:%d, err\n", __func__, __LINE__);
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- sbi_hart_hang();
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- }
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+// if (rc != PSCI_E_DENIED) {
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+// sbi_printf("%s:%d, err\n", __func__, __LINE__);
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+// sbi_hart_hang();
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+// }
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return rc;
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}
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diff --git a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
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index 94d53bf51d0f..f87bacc7297d 100644
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--- a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
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+++ b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
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@@ -30,7 +30,8 @@ void spacemit_top_on(u_register_t mpidr)
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(1 << CLUSTER_BIT14_OFFSET) |
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(1 << CLUSTER_BIT30_OFFSET) |
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(1 << CLUSTER_BIT25_OFFSET) |
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- (1 << CLUSTER_BIT13_OFFSET));
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+ (1 << CLUSTER_BIT13_OFFSET) |
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+ (1 << CLUSTER_VOTE_AP_SLPEN));
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writel(value, cluster0_acpr);
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value = readl(cluster1_acpr);
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@@ -42,7 +43,8 @@ void spacemit_top_on(u_register_t mpidr)
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(1 << CLUSTER_BIT14_OFFSET) |
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(1 << CLUSTER_BIT30_OFFSET) |
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(1 << CLUSTER_BIT25_OFFSET) |
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- (1 << CLUSTER_BIT13_OFFSET));
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+ (1 << CLUSTER_BIT13_OFFSET) |
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+ (1 << CLUSTER_VOTE_AP_SLPEN));
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writel(value, cluster1_acpr);
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}
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@@ -60,7 +62,7 @@ void spacemit_top_off(u_register_t mpidr)
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(1 << CLUSTER_DDRSD_OFFSET) |
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(1 << CLUSTER_APBSD_OFFSET) |
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(1 << CLUSTER_VCXOSD_OFFSET) |
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- (1 << 3) |
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+ (1 << CLUSTER_VOTE_AP_SLPEN) |
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(1 << CLUSTER_BIT29_OFFSET) |
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(1 << CLUSTER_BIT14_OFFSET) |
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(1 << CLUSTER_BIT30_OFFSET) |
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@@ -73,7 +75,7 @@ void spacemit_top_off(u_register_t mpidr)
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(1 << CLUSTER_DDRSD_OFFSET) |
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(1 << CLUSTER_APBSD_OFFSET) |
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(1 << CLUSTER_VCXOSD_OFFSET) |
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- (1 << 3) |
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+ (1 << CLUSTER_VOTE_AP_SLPEN) |
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(1 << CLUSTER_BIT29_OFFSET) |
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(1 << CLUSTER_BIT14_OFFSET) |
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(1 << CLUSTER_BIT30_OFFSET) |
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@@ -279,6 +281,82 @@ void spacemit_wakeup_cpu(u_register_t mpidr)
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writel(1 << target_cpu_idx, cpu_reset_base);
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}
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+int spacemit_core_enter_c2(u_register_t mpidr)
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+{
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+ unsigned int value;
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+
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+ /* wait the cpu enter c2 */
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+ value = readl((unsigned int *)0xd4282890);
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+
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+ if (mpidr == 0) {
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+ if (value & (1 << 6))
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+ return 1;
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+ } else if (mpidr == 1) {
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+ if (value & (1 << 9))
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+ return 1;
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+ } else if (mpidr == 2) {
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+ if (value & (1 << 12))
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+ return 1;
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+ } else if (mpidr == 3) {
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+ if (value & (1 << 15))
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+ return 1;
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+ } else if (mpidr == 4) {
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+ if (value & (1 << 22))
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+ return 1;
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+ } else if (mpidr == 5) {
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+ if (value & (1 << 25))
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+ return 1;
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+ } else if (mpidr == 6) {
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+ if (value & (1 << 28))
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+ return 1;
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+ } else if (mpidr == 7) {
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+ if (value & (1 << 31))
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+ return 1;
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+ } else {
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+ return 0;
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+ }
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+
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+ return 0;
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+}
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+
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+void spacemit_wait_core_enter_c2(u_register_t mpidr)
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+{
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+ unsigned int value;
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+
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+ while (1) {
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+ /* wait the cpu enter c2 */
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+ value = readl((unsigned int *)0xd4282890);
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+
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+ if (mpidr == 0) {
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+ if (value & (1 << 6))
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+ return;
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+ } else if (mpidr == 1) {
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+ if (value & (1 << 9))
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+ return;
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+ } else if (mpidr == 2) {
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+ if (value & (1 << 12))
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+ return;
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+ } else if (mpidr == 3) {
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+ if (value & (1 << 15))
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+ return;
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+ } else if (mpidr == 4) {
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+ if (value & (1 << 22))
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+ return;
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+ } else if (mpidr == 5) {
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+ if (value & (1 << 25))
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+ return;
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+ } else if (mpidr == 6) {
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+ if (value & (1 << 28))
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+ return;
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+ } else if (mpidr == 7) {
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+ if (value & (1 << 31))
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+ return;
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+ } else {
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+ ;
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+ }
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+ }
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+}
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+
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void spacemit_assert_cpu(u_register_t mpidr)
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{
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unsigned int target_cpu_idx;
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diff --git a/lib/utils/psci/spacemit/plat/plat_pm.c b/lib/utils/psci/spacemit/plat/plat_pm.c
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index a5b91270834f..166bc3c7be1f 100644
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--- a/lib/utils/psci/spacemit/plat/plat_pm.c
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+++ b/lib/utils/psci/spacemit/plat/plat_pm.c
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@@ -1,14 +1,20 @@
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#include <sbi/sbi_types.h>
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+#include <sbi/riscv_locks.h>
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#include <sbi/riscv_asm.h>
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#include <sbi_utils/cci/cci.h>
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#include <sbi_utils/psci/psci.h>
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#include <sbi/sbi_scratch.h>
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+#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_hart.h>
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+#include <sbi/sbi_hsm.h>
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+#include <sbi/sbi_domain.h>
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#include <sbi/sbi_console.h>
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+#include <sbi/sbi_hartmask.h>
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#include <sbi_utils/psci/plat/arm/common/arm_def.h>
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#include <sbi_utils/irqchip/fdt_irqchip_plic.h>
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#include <sbi_utils/cache/cacheflush.h>
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#include "underly_implement.h"
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+#include "../../psci_private.h"
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#define CORE_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL0])
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@@ -20,17 +26,39 @@
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/* reserved for future used */
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/* unsigned long __plic_regsave_offset_ptr; */
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+static spinlock_t psciipi_lock = SPIN_LOCK_INITIALIZER;
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+static struct sbi_hartmask psciipi_wait_hmask = { 0 };
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+
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+static void wake_idle_harts(struct sbi_scratch *scratch, u32 hartid)
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+{
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+ spin_lock(&psciipi_lock);
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+
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+ /* Send an IPI to all HARTs of the cluster that waiting for waked up */
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+ for (u32 i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_CLUSTER_COUNT; i++) {
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+ if (i != hartid) {
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+ sbi_hartmask_set_hart(i, &psciipi_wait_hmask);
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+ sbi_ipi_raw_send(i);
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+ }
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+ }
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+
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+ spin_unlock(&psciipi_lock);
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+}
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+
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static int spacemit_pwr_domain_on(u_register_t mpidr)
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{
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/* wakeup the cpu */
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- spacemit_wakeup_cpu(mpidr);
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+ if (spacemit_core_enter_c2(mpidr)) {
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+ spacemit_wakeup_cpu(mpidr);
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+ } else {
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+ sbi_ipi_raw_send(mpidr);
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+ }
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return 0;
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}
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static void spacemit_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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- unsigned int hartid = current_hartid();
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+ unsigned int hartid = current_hartid();
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if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
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/* D1P */
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@@ -42,12 +70,12 @@ static void spacemit_pwr_domain_on_finish(const psci_power_state_t *target_state
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* No need for locks as no other cpu is active at the moment.
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*/
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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- spacemit_cluster_on(hartid);
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+ spacemit_cluster_on(hartid);
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#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
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/* disable the tcm */
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csr_write(CSR_TCMCFG, 0);
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#endif
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- cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(hartid));
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+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(hartid));
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#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
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/* enable the tcm */
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csr_write(CSR_TCMCFG, 1);
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@@ -62,6 +90,7 @@ static int spacemit_pwr_domain_off_early(const psci_power_state_t *target_state)
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/* clear the external irq pending */
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csr_clear(CSR_MIP, MIP_MEIP);
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csr_clear(CSR_MIP, MIP_SEIP);
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+ csr_clear(CSR_MIP, MIP_MSIP);
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/* here we clear the sstimer pending if this core have */
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if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(), SBI_HART_EXT_SSTC)) {
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@@ -76,28 +105,65 @@ static void spacemit_pwr_domain_off(const psci_power_state_t *target_state)
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unsigned int hartid = current_hartid();
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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-#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
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- /* disable the tcm */
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- csr_write(CSR_TCMCFG, 0);
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-#endif
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- cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(hartid));
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- spacemit_cluster_off(hartid);
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- csi_flush_l2_cache(1);
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+ /* power-off cluster */
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+ spacemit_cluster_off(hartid);
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}
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if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
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/* D1P */
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spacemit_top_off(hartid);
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}
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-
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- spacemit_assert_cpu(hartid);
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}
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static void spacemit_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
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{
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- while (1) {
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- asm volatile ("wfi");
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+ int hstate;
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+ unsigned long saved_mie, cmip;
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+ unsigned int hartid = current_hartid();
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+
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+ hstate = sbi_hsm_hart_get_state(sbi_domain_thishart_ptr(), hartid);
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+
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+ /* Save MIE CSR */
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+ saved_mie = csr_read(CSR_MIE);
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+
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+ /* Set MSIE and MEIE bits to receive IPI */
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+ if (hstate == SBI_HSM_STATE_SUSPENDED) {
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+ csr_set(CSR_MIE, MIP_MSIP | MIP_MEIP);
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+
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+ /* Wait for wakeup source to finish using WFI */
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+ do {
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+ wfi();
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+ cmip = csr_read(CSR_MIP);
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+ } while (!(cmip & (MIP_MSIP | MIP_MEIP)));
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+ } else {
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+ csr_set(CSR_MIE, MIP_MSIP);
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+
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+ /* Wait for wakeup source to finish using WFI */
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+ do {
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+ wfi();
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+ cmip = csr_read(CSR_MIP);
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+ } while (!(cmip & (MIP_MSIP)));
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+
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+ spin_lock(&psciipi_lock);
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+
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+ if (sbi_hartmask_test_hart(hartid, &psciipi_wait_hmask)) {
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+ sbi_ipi_raw_clear(hartid);
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+ /* Restore MIE CSR */
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+ csr_write(CSR_MIE, saved_mie);
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+
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+ spin_unlock(&psciipi_lock);
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+
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+ spacemit_assert_cpu(hartid);
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+
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+ while (1)
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+ asm volatile ("wfi");
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+ }
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+
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+ spin_unlock(&psciipi_lock);
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}
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+
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+ /* Restore MIE CSR */
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+ csr_write(CSR_MIE, saved_mie);
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}
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static void spacemit_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
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@@ -158,9 +224,8 @@ static int spacemit_validate_power_state(unsigned int power_state,
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static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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- unsigned int clusterid;
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unsigned int hartid = current_hartid();
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-
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+
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/*
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* CSS currently supports retention only at cpu level. Just return
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* as nothing is to be done for retention.
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@@ -168,30 +233,40 @@ static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
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if (CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
|
|
return;
|
|
|
|
-
|
|
if (CORE_PWR_STATE(target_state) != ARM_LOCAL_STATE_OFF) {
|
|
sbi_printf("%s:%d\n", __func__, __LINE__);
|
|
sbi_hart_hang();
|
|
}
|
|
|
|
- /* Cluster is to be turned off, so disable coherency */
|
|
- if (CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
|
|
- clusterid = MPIDR_AFFLVL1_VAL(hartid);
|
|
+ /* power-off cluster */
|
|
+ if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
|
|
+ spacemit_cluster_off(hartid);
|
|
+
|
|
+ if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
|
|
#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
|
|
/* disable the tcm */
|
|
csr_write(CSR_TCMCFG, 0);
|
|
#endif
|
|
- cci_disable_snoop_dvm_reqs(clusterid);
|
|
- spacemit_cluster_off(hartid);
|
|
- csi_flush_l2_cache(1);
|
|
- }
|
|
+ wake_idle_harts(NULL, hartid);
|
|
|
|
- if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
|
|
/* D1P & D2 */
|
|
+ csi_flush_l2_cache_hart(0, 0);
|
|
+ csi_flush_l2_cache_hart(0, PLATFORM_MAX_CPUS_PER_CLUSTER);
|
|
+
|
|
+ cci_disable_snoop_dvm_reqs(0);
|
|
+ cci_disable_snoop_dvm_reqs(1);
|
|
+
|
|
+ /* assert othter cpu & wait other cpu enter c2 */
|
|
+ for (u32 i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_CLUSTER_COUNT; i++) {
|
|
+ if (i != hartid) {
|
|
+ spacemit_wait_core_enter_c2(i);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ spacemit_assert_cpu(hartid);
|
|
+
|
|
spacemit_top_off(hartid);
|
|
}
|
|
-
|
|
- spacemit_assert_cpu(hartid);
|
|
}
|
|
|
|
static void spacemit_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
|
|
diff --git a/lib/utils/psci/spacemit/plat/underly_implement.h b/lib/utils/psci/spacemit/plat/underly_implement.h
|
|
index dd6c972325bb..7c11db518a3f 100644
|
|
--- a/lib/utils/psci/spacemit/plat/underly_implement.h
|
|
+++ b/lib/utils/psci/spacemit/plat/underly_implement.h
|
|
@@ -9,6 +9,8 @@ void spacemit_cluster_on(u_register_t mpidr);
|
|
void spacemit_cluster_off(u_register_t mpidr);
|
|
void spacemit_wakeup_cpu(u_register_t mpidr);
|
|
void spacemit_assert_cpu(u_register_t mpidr);
|
|
+int spacemit_core_enter_c2(u_register_t mpidr);
|
|
+void spacemit_wait_core_enter_c2(u_register_t mpidr);
|
|
void spacemit_deassert_cpu(void);
|
|
|
|
#endif
|
|
diff --git a/lib/utils/serial/fdt_serial_uart8250.c b/lib/utils/serial/fdt_serial_uart8250.c
|
|
index 7b5d6a4c2f18..51ea91c7665f 100644
|
|
--- a/lib/utils/serial/fdt_serial_uart8250.c
|
|
+++ b/lib/utils/serial/fdt_serial_uart8250.c
|
|
@@ -30,6 +30,7 @@ static const struct fdt_match serial_uart8250_match[] = {
|
|
{ .compatible = "ns16550" },
|
|
{ .compatible = "ns16550a" },
|
|
{ .compatible = "snps,dw-apb-uart" },
|
|
+ { .compatible = "spacemit,pxa-uart" },
|
|
{ },
|
|
};
|
|
|
|
diff --git a/platform/generic/include/spacemit/k1x/k1x_evb.h b/platform/generic/include/spacemit/k1x/k1x_evb.h
|
|
index 10e856965618..e7381ca245da 100644
|
|
--- a/platform/generic/include/spacemit/k1x/k1x_evb.h
|
|
+++ b/platform/generic/include/spacemit/k1x/k1x_evb.h
|
|
@@ -60,6 +60,7 @@
|
|
#define CLUSTER_BIT30_OFFSET (30)
|
|
#define CLUSTER_BIT25_OFFSET (25)
|
|
#define CLUSTER_BIT13_OFFSET (13)
|
|
+#define CLUSTER_VOTE_AP_SLPEN (3)
|
|
|
|
#define L2_HARDWARE_CACHE_FLUSH_EN (13)
|
|
|
|
diff --git a/platform/generic/spacemit/spacemit_k1.c b/platform/generic/spacemit/spacemit_k1.c
|
|
index 95218846715f..2f9deb1a7940 100644
|
|
--- a/platform/generic/spacemit/spacemit_k1.c
|
|
+++ b/platform/generic/spacemit/spacemit_k1.c
|
|
@@ -67,15 +67,15 @@ static void wakeup_other_core(void)
|
|
|
|
#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
|
|
/* enable the hw l2 cache flush method for each core */
|
|
- writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG0);
|
|
- writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG1);
|
|
- writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG2);
|
|
- writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG3);
|
|
-
|
|
- writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG0);
|
|
- writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG1);
|
|
- writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG2);
|
|
- writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG3);
|
|
+ /* writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG0); */
|
|
+ /* writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG1); */
|
|
+ /* writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG2); */
|
|
+ /* writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG3); */
|
|
+
|
|
+ /* writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG0); */
|
|
+ /* writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG1); */
|
|
+ /* writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG2); */
|
|
+ /* writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG3); */
|
|
#endif
|
|
|
|
// hart0 is already boot up
|
|
@@ -188,7 +188,8 @@ static int spacemit_hart_start(unsigned int hartid, unsigned long saddr)
|
|
static int spacemit_hart_stop(void)
|
|
{
|
|
psci_cpu_off();
|
|
- return 0;
|
|
+
|
|
+ return SBI_ENOTSUPP;
|
|
}
|
|
|
|
static int spacemit_hart_suspend(unsigned int suspend_type)
|
|
@@ -265,6 +266,8 @@ static bool spacemit_cold_boot_allowed(u32 hartid, const struct fdt_match *match
|
|
static const struct fdt_match spacemit_k1_match[] = {
|
|
{ .compatible = "spacemit,k1-pro" },
|
|
{ .compatible = "spacemit,k1x" },
|
|
+ { .compatible = "spacemit,k1-x" },
|
|
+ { .compatible = "spacemit,k1" },
|
|
{ },
|
|
};
|
|
|
|
--
|
|
2.35.3
|
|
|