70 lines
1.7 KiB
Diff
70 lines
1.7 KiB
Diff
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -8,9 +8,19 @@
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/ {
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compatible = "rockchip,rk3568";
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- pipe_phy_grf0: syscon@fdc70000 {
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- compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
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- reg = <0x0 0xfdc70000 0x0 0x1000>;
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+ sata0: sata@fc000000 {
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+ compatible = "snps,dwc-ahci";
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+ reg = <0 0xfc000000 0 0x1000>;
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+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
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+ <&cru CLK_SATA0_RXOOB>;
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+ clock-names = "sata", "pmalive", "rxoob";
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+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hostc";
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+ phys = <&combphy0 PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ ports-implemented = <0x1>;
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ status = "disabled";
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};
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qos_pcie3x1: qos@fe190080 {
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@@ -76,22 +86,6 @@
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queue0 {};
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};
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};
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-
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- combphy0: phy@fe820000 {
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- compatible = "rockchip,rk3568-naneng-combphy";
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- reg = <0x0 0xfe820000 0x0 0x100>;
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- clocks = <&pmucru CLK_PCIEPHY0_REF>,
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- <&cru PCLK_PIPEPHY0>,
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- <&cru PCLK_PIPE>;
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- clock-names = "ref", "apb", "pipe";
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- assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
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- assigned-clock-rates = <100000000>;
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- resets = <&cru SRST_PIPEPHY0>;
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- rockchip,pipe-grf = <&pipegrf>;
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- rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
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- #phy-cells = <1>;
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- status = "disabled";
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- };
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};
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&cpu0_opp_table {
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@@ -99,6 +93,10 @@
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opp-hz = /bits/ 64 <1992000000>;
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opp-microvolt = <1150000 1150000 1150000>;
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};
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+};
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+
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+&pipegrf {
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+ compatible = "rockchip,rk3568-pipegrf", "syscon";
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};
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&power {
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@@ -120,3 +118,8 @@
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&vop {
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compatible = "rockchip,rk3568-vop";
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};
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+
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+&usbdrd_dwc3 {
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+ phys = <&u2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+};
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