d3f1018026
4.13 rc4 brought some changes to the rk3288 dtsi, it mangled up the patches carried over from 4.12
98 lines
2.9 KiB
Diff
98 lines
2.9 KiB
Diff
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index fc2d6be..624416f 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -1143,6 +1143,92 @@
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};
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};
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+ vpu: video-codec@ff9a0000 {
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+ compatible = "rockchip,rk3288-vpu";
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+ reg = <0xff9a0000 0x800>;
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+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "vepu", "vdpu";
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+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
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+ clock-names = "aclk", "hclk";
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+ power-domains = <&power RK3288_PD_VIDEO>;
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+ iommus = <&vpu_mmu>;
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+ assigned-clocks = <&cru ACLK_VCODEC>;
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+ assigned-clock-rates = <400000000>;
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+ status = "disabled";
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+ };
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+
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+ vpu_service: vpu-service@ff9a0000 {
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+ compatible = "rockchip,vpu_service";
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+ reg = <0xff9a0000 0x800>;
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+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "irq_enc", "irq_dec";
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+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
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+ clock-names = "aclk_vcodec", "hclk_vcodec";
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+ power-domains = <&power RK3288_PD_VIDEO>;
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+ rockchip,grf = <&grf>;
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+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
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+ reset-names = "video_a", "video_h";
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+ iommus = <&vpu_mmu>;
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+ iommu_enabled = <1>;
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+ dev_mode = <0>;
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+ status = "disabled";
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+ /* 0 means ion, 1 means drm */
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+ allocator = <1>;
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+ };
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+
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+ vpu_mmu: iommu@ff9a0800 {
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+ compatible = "rockchip,iommu";
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+ reg = <0xff9a0800 0x100>;
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+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "vpu_mmu";
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+ power-domains = <&power RK3288_PD_VIDEO>;
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+ #iommu-cells = <0>;
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+ };
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+
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+ hevc_service: hevc-service@ff9c0000 {
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+ compatible = "rockchip,hevc_service";
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+ reg = <0xff9c0000 0x400>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "irq_dec";
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+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
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+ <&cru SCLK_HEVC_CORE>,
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+ <&cru SCLK_HEVC_CABAC>;
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+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
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+ "clk_cabac";
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+ /*
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+ * The 4K hevc would also work well with 500/125/300/300,
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+ * no more err irq and reset request.
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+ */
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+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
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+ <&cru SCLK_HEVC_CORE>,
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+ <&cru SCLK_HEVC_CABAC>;
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+ assigned-clock-rates = <400000000>, <100000000>,
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+ <300000000>, <300000000>;
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+
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+ resets = <&cru SRST_HEVC>;
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+ reset-names = "video";
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+ power-domains = <&power RK3288_PD_HEVC>;
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+ rockchip,grf = <&grf>;
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+ dev_mode = <1>;
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+ iommus = <&hevc_mmu>;
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+ iommu_enabled = <1>;
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+ status = "disabled";
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+ /* 0 means ion, 1 means drm */
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+ allocator = <1>;
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+ };
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+
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+ hevc_mmu: iommu@ff9c0440 {
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+ compatible = "rockchip,iommu";
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+ reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
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+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hevc_mmu";
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+ power-domains = <&power RK3288_PD_HEVC>;
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+ #iommu-cells = <0>;
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+ };
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+
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+
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gpu: gpu@ffa30000 {
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compatible = "rockchip,rk3288-mali", "arm,mali-t760";
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reg = <0xffa30000 0x10000>;
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