41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
From 7e83be2067e27dfb7badcf06563d67d22c44089b Mon Sep 17 00:00:00 2001
|
|
From: LABBE Corentin <clabbe.montjoie@gmail.com>
|
|
Date: Mon, 4 Apr 2016 16:04:39 +0200
|
|
Subject: [PATCH] ARM: sun8i: dt: enable Add Crypto Engine on H3
|
|
|
|
The Crypto Engine is a hardware cryptographic accelerator that support
|
|
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
|
|
It could be found on Allwinner SoC H3 and A64.
|
|
|
|
This patch enable the Crypto Engine on the Allwinner H3 SoC Device-tree.
|
|
|
|
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
|
|
---
|
|
arch/arm/boot/dts/sun8i-h3.dtsi | 13 +++++++++++++
|
|
1 file changed, 13 insertions(+)
|
|
|
|
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
|
|
index cc2a8b4..d89b254 100644
|
|
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
|
|
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
|
|
@@ -571,6 +571,19 @@
|
|
};
|
|
};
|
|
|
|
+ crypto: crypto@1c15000 {
|
|
+ compatible = "allwinner,sun8i-h3-crypto";
|
|
+ reg = <0x01c15000 0x1000>;
|
|
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "ce_s", "ce_ns";
|
|
+ resets = <&ccu RST_BUS_CE>;
|
|
+ reset-names = "ahb";
|
|
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
|
|
+ clock-names = "ahb1_ce", "mod";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|