78d28f8083
1, format all patches from https://github.com/megous/linux `git format-patch 79bf89b88a87f2ebf147f76d8c40183283b49b51...2a7cb228d29c3882c1414c10a44c5f3f59bfa44d` and copy them to sunxi-next with prefix `0000-` 2, remove unnecessary patches, due to they are revert of upstream patches:4d867e2bd64e674a3000b8e05fe47e8bb8175edda2888276ee3, remove fail to apply and no use:960ddd63a84, remove WireGuard patch:1cd13b836c5, remove meaningless patch:f26e36379a6, remove merged or included by megous/linux patches: 0112-mfd-axp20x-Add-supported-cells-for-AXP803.patch board-bpi-m3-make-ethernet-working.patch board-pine-h6-pine-h6-0025-phy-sun4i-usb-add-support-for-missing-USB-PHY-index.patch 7, remove stable release update patches. ignored. 8, rebase sunxi-next/sunxi64-next to upstream linux-4.19.y test result: all patches applied, no error. orangepipc/orangpioneplus build OK. Signed-off-by: Zhang Ning <832666+zhangn1985@users.noreply.github.com>
83 lines
2.3 KiB
Diff
83 lines
2.3 KiB
Diff
From 0ab580b2eac299d7f73c2ff3e7bf590a3fc7ea6d Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Fri, 20 Apr 2018 04:05:28 +0200
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Subject: [PATCH 68/82] ARM: dts: sun8i-a83t: Add clock-frequency to avoid boot
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warnings
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
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index bffcee058627..c09d8ee2f7c5 100644
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--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
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+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
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@@ -65,6 +65,7 @@
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clocks = <&ccu CLK_C0CPUX>;
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clock-names = "cpu";
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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cci-control-port = <&cci_control0>;
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@@ -77,6 +78,7 @@
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cpu@1 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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cci-control-port = <&cci_control0>;
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@@ -86,6 +88,7 @@
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cpu@2 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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cci-control-port = <&cci_control0>;
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@@ -95,6 +98,7 @@
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cpu@3 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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cci-control-port = <&cci_control0>;
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@@ -106,6 +110,7 @@
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clocks = <&ccu CLK_C1CPUX>;
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clock-names = "cpu";
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu1_opp_table>;
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cci-control-port = <&cci_control1>;
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@@ -118,6 +123,7 @@
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cpu@101 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu1_opp_table>;
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cci-control-port = <&cci_control1>;
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@@ -127,6 +133,7 @@
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cpu@102 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu1_opp_table>;
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cci-control-port = <&cci_control1>;
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@@ -136,6 +143,7 @@
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cpu@103 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu1_opp_table>;
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cci-control-port = <&cci_control1>;
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--
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2.20.1
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