48 lines
1.8 KiB
Diff
48 lines
1.8 KiB
Diff
From 3b5196142b543e34baab184671f41785177a67d7 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Mon, 27 Mar 2017 23:06:12 +0200
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Subject: [PATCH] edid: Set timings flags according to edid
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Timing flags are never set, so they may contain garbage. Since some
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drivers check them, video output may be broken on those drivers.
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Initialize them to 0 and check for few common flags.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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common/edid.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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diff --git a/common/edid.c b/common/edid.c
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index e08e420..ab7069f 100644
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--- a/common/edid.c
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+++ b/common/edid.c
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@@ -85,6 +85,7 @@ static void decode_timing(u8 *buf, struct display_timing *timing)
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uint x_mm, y_mm;
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unsigned int ha, hbl, hso, hspw, hborder;
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unsigned int va, vbl, vso, vspw, vborder;
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+ struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf;
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/* Edid contains pixel clock in terms of 10KHz */
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set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000);
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@@ -111,6 +112,19 @@ static void decode_timing(u8 *buf, struct display_timing *timing)
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set_entry(&timing->vback_porch, vbl - vso - vspw);
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set_entry(&timing->vsync_len, vspw);
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+ timing->flags = 0;
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+ if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t))
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+ timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
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+ else
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+ timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
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+ if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t))
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+ timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
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+ else
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+ timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
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+
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+ if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t))
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+ timing->flags = DISPLAY_FLAGS_INTERLACED;
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+
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debug("Detailed mode clock %u Hz, %d mm x %d mm\n"
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" %04x %04x %04x %04x hborder %x\n"
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" %04x %04x %04x %04x vborder %x\n",
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