167 lines
4.6 KiB
Diff
167 lines
4.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Xilin Wu <wuxilin123@gmail.com>
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Date: Fri, 23 May 2025 21:10:39 +0800
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Subject: arm64: qcom: sc7280: Add PCIe0 controller
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Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
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---
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arch/arm64/boot/dts/qcom/sc7280.dtsi | 128 +++++++++-
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1 file changed, 127 insertions(+), 1 deletion(-)
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diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
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index 111111111111..222222222222 100644
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--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
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+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
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@@ -971,7 +971,7 @@ gcc: clock-controller@100000 {
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reg = <0 0x00100000 0 0x1f0000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
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- <0>, <&pcie1_phy>,
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+ <&pcie0_phy>, <&pcie1_phy>,
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<&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
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<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
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@@ -2201,6 +2201,127 @@ wifi: wifi@17a10040 {
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qcom,smem-state-names = "wlan-smp2p-out";
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};
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+ pcie0: pcie@1c00000 {
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+ compatible = "qcom,pcie-sc7280";
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+ reg = <0 0x01c00000 0 0x3000>,
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+ <0 0x60000000 0 0xf1d>,
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+ <0 0x60000f20 0 0xa8>,
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+ <0 0x60001000 0 0x1000>,
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+ <0 0x60100000 0 0x100000>;
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+
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+ reg-names = "parf", "dbi", "elbi", "atu", "config";
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
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+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
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+
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
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+
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+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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+ <&pcie0_phy>,
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+ <&rpmhcc RPMH_CXO_CLK>,
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+ <&gcc GCC_PCIE_0_AUX_CLK>,
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+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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+ <&gcc GCC_DDRSS_PCIE_SF_CLK>,
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+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
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+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
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+
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+ clock-names = "pipe",
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+ "pipe_mux",
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+ "phy_pipe",
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+ "ref",
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+ "aux",
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+ "cfg",
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+ "bus_master",
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+ "bus_slave",
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+ "slave_q2a",
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+ "tbu",
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+ "ddrss_sf_tbu",
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+ "aggre0",
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+ "aggre1";
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+
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+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
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+ assigned-clock-rates = <19200000>;
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+
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+ resets = <&gcc GCC_PCIE_0_BCR>;
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+ reset-names = "pci";
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+
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+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
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+
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+ phys = <&pcie0_phy>;
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+ phy-names = "pciephy";
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie0_clkreq_n>;
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+
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+ dma-coherent;
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+
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+ interconnects = <&aggre1_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
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+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_PCIE_0 0>;
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+ interconnect-names = "pcie-mem", "cpu-pcie";
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+
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+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
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+ <0x100 &apps_smmu 0x1c01 0x1>;
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+
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+ status = "disabled";
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+
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+ pcie@0 {
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+ device_type = "pci";
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+ reg = <0x0 0x0 0x0 0x0 0x0>;
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+ bus-range = <0x01 0xff>;
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ ranges;
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+ };
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+ };
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+
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+ pcie0_phy: phy@1c06000 {
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+ compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
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+ reg = <0 0x01c06000 0 0x1c0>;
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+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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+ <&gcc GCC_PCIE_CLKREF_EN>,
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+ <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
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+ <&gcc GCC_PCIE_0_PIPE_CLK>;
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+ clock-names = "aux",
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+ "cfg_ahb",
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+ "ref",
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+ "refgen",
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+ "pipe";
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+
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+ clock-output-names = "pcie_0_pipe_clk";
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+ #clock-cells = <0>;
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+
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+ #phy-cells = <0>;
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+
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+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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+ reset-names = "phy";
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+
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+ assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
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+ assigned-clock-rates = <100000000>;
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+
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+ status = "disabled";
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+ };
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+
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pcie1: pcie@1c08000 {
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compatible = "qcom,pcie-sc7280";
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reg = <0 0x01c08000 0 0x3000>,
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@@ -5372,6 +5493,11 @@ mi2s1_ws: mi2s1-ws-state {
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function = "mi2s1_ws";
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};
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+ pcie0_clkreq_n: pcie0-clkreq-n-state {
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+ pins = "gpio88";
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+ function = "pcie0_clkreqn";
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+ };
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+
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pcie1_clkreq_n: pcie1-clkreq-n-state {
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pins = "gpio79";
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function = "pcie1_clkreqn";
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--
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Armbian
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