120 lines
4.1 KiB
Diff
120 lines
4.1 KiB
Diff
From patchwork Tue Oct 27 16:50:21 2015
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v4,
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1/6] clk: sunxi: Let divs clocks read the base factor clock name from
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devicetree
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From: Jens Kuske <jenskuske@gmail.com>
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X-Patchwork-Id: 7498741
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Message-Id: <1445964626-6484-2-git-send-email-jenskuske@gmail.com>
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To: Maxime Ripard <maxime.ripard@free-electrons.com>,
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Chen-Yu Tsai <wens@csie.org>, Michael Turquette <mturquette@baylibre.com>,
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Linus Walleij <linus.walleij@linaro.org>,
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Rob Herring <robh+dt@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>,
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=?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Cc: devicetree@vger.kernel.org, Vishnu Patekar <vishnupatekar0510@gmail.com>,
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linux-kernel@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>,
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linux-sunxi@googlegroups.com, Jens Kuske <jenskuske@gmail.com>,
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linux-arm-kernel@lists.infradead.org
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Date: Tue, 27 Oct 2015 17:50:21 +0100
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Currently, the sunxi clock driver gets the name for the base factor clock
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of divs clocks from the name field in factors_data. This prevents reusing
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of the factor clock for clocks with same properties, but different name.
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This commit makes the divs setup function try to get a name from
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clock-output-names in the devicetree. It also removes the name field where
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possible and merges the sun4i PLL5 and PLL6 clocks.
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Signed-off-by: Jens Kuske <jenskuske@gmail.com>
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---
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drivers/clk/sunxi/clk-sunxi.c | 38 +++++++++++++++++++++++++++-----------
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1 file changed, 27 insertions(+), 11 deletions(-)
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index 9c79af0c..270de42 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -704,21 +704,12 @@ static const struct factors_data sun4i_pll5_data __initconst = {
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.enable = 31,
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.table = &sun4i_pll5_config,
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.getter = sun4i_get_pll5_factors,
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- .name = "pll5",
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-};
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-
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-static const struct factors_data sun4i_pll6_data __initconst = {
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- .enable = 31,
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- .table = &sun4i_pll5_config,
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- .getter = sun4i_get_pll5_factors,
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- .name = "pll6",
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};
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static const struct factors_data sun6i_a31_pll6_data __initconst = {
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.enable = 31,
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.table = &sun6i_a31_pll6_config,
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.getter = sun6i_a31_get_pll6_factors,
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- .name = "pll6x2",
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};
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static const struct factors_data sun5i_a13_ahb_data __initconst = {
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@@ -902,6 +893,7 @@ struct gates_data {
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#define SUNXI_DIVS_MAX_QTY 4
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#define SUNXI_DIVISOR_WIDTH 2
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+#define SUNXI_DIVS_BASE_NAME_MAX_LEN 8
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struct divs_data {
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const struct factors_data *factors; /* data for the factor clock */
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@@ -941,7 +933,7 @@ static const struct divs_data pll5_divs_data __initconst = {
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};
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static const struct divs_data pll6_divs_data __initconst = {
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- .factors = &sun4i_pll6_data,
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+ .factors = &sun4i_pll5_data,
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.ndivs = 4,
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.div = {
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{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
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@@ -983,6 +975,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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struct clk_gate *gate = NULL;
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struct clk_fixed_factor *fix_factor;
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struct clk_divider *divider;
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+ struct factors_data factors = *data->factors;
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+ char base_name[SUNXI_DIVS_BASE_NAME_MAX_LEN];
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void __iomem *reg;
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int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
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int flags, clkflags;
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@@ -991,8 +985,30 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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if (data->ndivs)
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ndivs = data->ndivs;
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+ /* Try to find a name for base factor clock */
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+ for (i = 0; i < ndivs; i++) {
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+ if (data->div[i].self) {
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+ of_property_read_string_index(node, "clock-output-names",
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+ i, &factors.name);
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+ break;
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+ }
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+ }
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+ /* If we don't have a .self clk use the first output-name up to '_' */
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+ if (factors.name == NULL) {
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+ of_property_read_string_index(node, "clock-output-names",
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+ 0, &clk_name);
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+
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+ for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 &&
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+ clk_name[i] != '_' &&
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+ clk_name[i] != '\0'; i++)
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+ base_name[i] = clk_name[i];
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+
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+ base_name[i] = '\0';
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+ factors.name = base_name;
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+ }
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+
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/* Set up factor clock that we will be dividing */
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- pclk = sunxi_factors_clk_setup(node, data->factors);
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+ pclk = sunxi_factors_clk_setup(node, &factors);
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parent = __clk_get_name(pclk);
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reg = of_iomap(node, 0);
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