42 lines
1.3 KiB
Diff
42 lines
1.3 KiB
Diff
From 1302d80e0ef39a0e27510259ee08f53d1c8e970e Mon Sep 17 00:00:00 2001
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From: scorpio_chang <Scorpio_Chang@asus.com>
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Date: Thu, 24 Aug 2017 10:17:35 +0800
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Subject: [PATCH] correct GPIO setting of UART4.
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Change-Id: If51a8779584fbd62b4744d9f13ced5a227dda225
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Reviewed-on: https://tp-biosrd-v02/gerrit/80325
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Reviewed-by: Scorpio Chang(張志賢) <Scorpio_Chang@asus.com>
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Tested-by: Scorpio Chang(張志賢) <Scorpio_Chang@asus.com>
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---
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arch/arm/boot/dts/rk3288.dtsi | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index 48ad3f3cab50..cc13411b7641 100755
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -2138,16 +2138,16 @@
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uart4 {
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uart4_xfer: uart4-xfer {
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- rockchip,pins = <5 12 3 &pcfg_pull_up>,
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- <5 13 3 &pcfg_pull_none>;
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+ rockchip,pins = <5 15 3 &pcfg_pull_up>,
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+ <5 14 3 &pcfg_pull_none>;
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};
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uart4_cts: uart4-cts {
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- rockchip,pins = <5 14 3 &pcfg_pull_up>;
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+ rockchip,pins = <5 12 3 &pcfg_pull_up>;
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};
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uart4_rts: uart4-rts {
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- rockchip,pins = <5 15 3 &pcfg_pull_none>;
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+ rockchip,pins = <5 13 3 &pcfg_pull_none>;
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};
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};
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