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armbian-build/patch/kernel/rk322x-dev/01-linux-0001-rockchip-from-5.9.patch
paolo bd17d4dbd0 Many changes for rk322x target: 
- Chanaged default x.org configuration to disable glamor
- Reintroduce patch to use DRM cursor plane as overlay in rk322x-current and -dev
- Updated wifi patches for kernel 5.8.10
- Bumped rk322x to u-boot v2020.07, removed reserved zones from device trees
- Updated OPTEE to v3.10, using ddrbin v1.10
- Bumped rk322x-current to kernel 5.8.y
- Imported new patches from knaerzche's LibreELEC fork for rk322x-dev (kernel 5.8.y)
- Adjusted existing patches to match changes, updated rk322x-dev kernel config file
- Add default modprobe conf file for esp8089 to force the crystal frequency to 40Mhz for rk322x targets
- Removed ssv6051 firmware packages to move to armbian-firmware repository
- Switching ssv6051-wifi.cfg to /lib/firmware for rk322x-legacy
- Removed P2P interface for esp8089 driver for rk322x-legacy
- Optimized ssv6051 performance: kernel module gains -Os flag, disabled p2p interface, enabled HW crypto for CCMP cipher
- Enabled remote control interface, IR GPIO kernel module and HDMI CEC modules
2020-09-19 15:20:16 +00:00

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From df792eba98fd6a729c254623ea28968f642efd1e Mon Sep 17 00:00:00 2001
From: Tobias Schramm <t.schramm@manjaro.org>
Date: Thu, 28 May 2020 19:25:50 +0200
Subject: [PATCH] arm64: dts: rockchip: add fuel gauge to Pinebook Pro dts
This commit adds cw2015 fuel gauge and battery to the Pinebook Pro dts.
Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Link: https://lore.kernel.org/r/20200528172550.2324722-2-t.schramm@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c7c4d698cd2882c4d095aeed43bbad6fc990e998)
---
.../boot/dts/rockchip/rk3399-pinebook-pro.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
index cb0245d2226d..8f5b2df01560 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
@@ -28,6 +28,13 @@ backlight: edp-backlight {
pwms = <&pwm0 0 740740 0>;
};
+ bat: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <9800000>;
+ voltage-max-design-microvolt = <4350000>;
+ voltage-min-design-microvolt = <3000000>;
+ };
+
edp_panel: edp-panel {
compatible = "boe,nv140fhmn49";
backlight = <&backlight>;
@@ -741,6 +748,24 @@ usbc_dp: endpoint {
};
};
};
+
+ cw2015@62 {
+ compatible = "cellwise,cw2015";
+ reg = <0x62>;
+ cellwise,battery-profile = /bits/ 8 <
+ 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
+ 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
+ 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
+ 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
+ 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
+ 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
+ 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
+ 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
+ >;
+ cellwise,monitor-interval-ms = <5000>;
+ monitored-battery = <&bat>;
+ power-supplies = <&mains_charger>, <&fusb0>;
+ };
};
&i2s1 {
From 279f038076d9ccc8a78c938eaf8008ff626ccb10 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 14 Jun 2020 14:29:51 +0000
Subject: [PATCH] arm64: dts: rockchip: set rockpro64 usbc dr_mode as host
The usb-c port on the rockpro64 does not detect devices reliably when in otg mode.
Setting the mode to "host" allows the port to work reliably.
This aligns with the pinebook-pro configuration.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20200614142950.1120694-1-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 75152d66315521a48c4997305f4e01c5f139e160)
---
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 6788ab28f89a..3456ee97c288 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -795,7 +795,7 @@ &usbdrd3_0 {
&usbdrd_dwc3_0 {
status = "okay";
- dr_mode = "otg";
+ dr_mode = "host";
};
&usbdrd3_1 {
From f739ccdaa19eac37af51d49e2d56e84b0bf62bfa Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx6244@gmail.com>
Date: Sun, 24 May 2020 18:06:36 +0200
Subject: [PATCH] arm64: dts: rockchip: rename label and nodename pinctrl
subnodes that end with gpio
A test with the command below gives for example this error:
arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dt.yaml:
tsadc: tsadc-otp-gpio:
{'phandle': [[90]], 'rockchip,pins': [[0, 6, 0, 123]]}
is not of type 'array'
'gpio' is a sort of reserved nodename and should not be used
for pinctrl in combination with 'rockchip,pins', so change
nodes that end with 'gpio' to end with 'pin' or 'pins'.
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/
dtschema/schemas/gpio/gpio.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200524160636.16547-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 2bc65fef4fe424f5f8295175f1b42f8b94c6df01)
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 6 +-
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 6 +-
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 2 +-
.../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 2 +-
.../arm64/boot/dts/rockchip/rk3328-rock64.dts | 2 +-
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 24 +++---
.../boot/dts/rockchip/rk3368-lion-haikou.dts | 2 +-
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 +-
.../boot/dts/rockchip/rk3399-firefly.dts | 4 +-
.../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 2 +-
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 4 +-
.../boot/dts/rockchip/rk3399-hugsun-x99.dts | 8 +-
.../boot/dts/rockchip/rk3399-leez-p710.dts | 8 +-
.../boot/dts/rockchip/rk3399-pinebook-pro.dts | 74 +++++++++----------
.../boot/dts/rockchip/rk3399-roc-pc.dtsi | 8 +-
.../boot/dts/rockchip/rk3399-rock-pi-4.dts | 8 +-
.../boot/dts/rockchip/rk3399-rock960.dtsi | 4 +-
.../boot/dts/rockchip/rk3399-rockpro64.dtsi | 8 +-
.../boot/dts/rockchip/rk3399-sapphire.dtsi | 4 +-
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +-
20 files changed, 94 insertions(+), 94 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index a6b8427156d5..e9bb2b97ae55 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -733,9 +733,9 @@ tsadc: tsadc@ff280000 {
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <120000>;
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&tsadc_otp_gpio>;
+ pinctrl-0 = <&tsadc_otp_pin>;
pinctrl-1 = <&tsadc_otp_out>;
- pinctrl-2 = <&tsadc_otp_gpio>;
+ pinctrl-2 = <&tsadc_otp_pin>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
@@ -1373,7 +1373,7 @@ i2c3_xfer: i2c3-xfer {
};
tsadc {
- tsadc_otp_gpio: tsadc-otp-gpio {
+ tsadc_otp_pin: tsadc-otp-pin {
rockchip,pins =
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index ac7f694079d0..ba1c71568164 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -1629,7 +1629,7 @@ spi2_mosi: spi2-mosi {
};
tsadc {
- tsadc_otp_gpio: tsadc-otp-gpio {
+ tsadc_otp_pin: tsadc-otp-pin {
rockchip,pins =
<0 RK_PB2 0 &pcfg_pull_none>;
};
@@ -1657,7 +1657,7 @@ uart0_rts: uart0-rts {
<2 RK_PA3 1 &pcfg_pull_none>;
};
- uart0_rts_gpio: uart0-rts-gpio {
+ uart0_rts_pin: uart0-rts-pin {
rockchip,pins =
<2 RK_PA3 0 &pcfg_pull_none>;
};
@@ -1730,7 +1730,7 @@ uart4_rts: uart4-rts {
<4 RK_PA7 1 &pcfg_pull_none>;
};
- uart4_rts_gpio: uart4-rts-gpio {
+ uart4_rts_pin: uart4-rts-pin {
rockchip,pins =
<4 RK_PA7 0 &pcfg_pull_none>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
index ac29c2744d08..1969dab84138 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -41,7 +41,7 @@ vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0m1_gpio>;
+ pinctrl-0 = <&sdmmc0m1_pin>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 34db48c274e5..b70ffb1c6a63 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -34,7 +34,7 @@ vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0m1_gpio>;
+ pinctrl-0 = <&sdmmc0m1_pin>;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 6e09c223ed57..86cfb5c50a94 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -25,7 +25,7 @@ vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0m1_gpio>;
+ pinctrl-0 = <&sdmmc0m1_pin>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index d399883d4b75..72e655020560 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -552,9 +552,9 @@ tsadc: tsadc@ff250000 {
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
rockchip,grf = <&grf>;
@@ -1154,7 +1154,7 @@ i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
<0 RK_PA6 2 &pcfg_pull_none>;
};
- i2c3_gpio: i2c3-gpio {
+ i2c3_pins: i2c3-pins {
rockchip,pins =
<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -1225,7 +1225,7 @@ pdmm0_fsync_sleep: pdmm0-fsync-sleep {
};
tsadc {
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -1248,7 +1248,7 @@ uart0_rts: uart0-rts {
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
};
- uart0_rts_gpio: uart0-rts-gpio {
+ uart0_rts_pin: uart0-rts-pin {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -1267,7 +1267,7 @@ uart1_rts: uart1-rts {
rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
};
- uart1_rts_gpio: uart1-rts-gpio {
+ uart1_rts_pin: uart1-rts-pin {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -1493,7 +1493,7 @@ sdmmc0m0_pwren: sdmmc0m0-pwren {
rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
};
- sdmmc0m0_gpio: sdmmc0m0-gpio {
+ sdmmc0m0_pin: sdmmc0m0-pin {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
@@ -1503,7 +1503,7 @@ sdmmc0m1_pwren: sdmmc0m1-pwren {
rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
};
- sdmmc0m1_gpio: sdmmc0m1-gpio {
+ sdmmc0m1_pin: sdmmc0m1-pin {
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
@@ -1536,7 +1536,7 @@ sdmmc0_bus4: sdmmc0-bus4 {
<1 RK_PA3 1 &pcfg_pull_up_8ma>;
};
- sdmmc0_gpio: sdmmc0-gpio {
+ sdmmc0_pins: sdmmc0-pins {
rockchip,pins =
<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
@@ -1578,7 +1578,7 @@ sdmmc0ext_bus4: sdmmc0ext-bus4 {
<3 RK_PA7 3 &pcfg_pull_up_4ma>;
};
- sdmmc0ext_gpio: sdmmc0ext-gpio {
+ sdmmc0ext_pins: sdmmc0ext-pins {
rockchip,pins =
<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
@@ -1623,7 +1623,7 @@ sdmmc1_bus4: sdmmc1-bus4 {
<1 RK_PC1 1 &pcfg_pull_up_8ma>;
};
- sdmmc1_gpio: sdmmc1-gpio {
+ sdmmc1_pins: sdmmc1-pins {
rockchip,pins =
<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
@@ -1817,7 +1817,7 @@ tsadc_pin {
tsadc_int: tsadc-int {
rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
};
- tsadc_gpio: tsadc-gpio {
+ tsadc_pin: tsadc-pin {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
index cbde279ae81d..dbd2caba322f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
@@ -125,7 +125,7 @@ led_sd_haikou: led-sd-gpio {
};
sdmmc {
- sdmmc_cd_gpio: sdmmc-cd-gpio {
+ sdmmc_cd_pin: sdmmc-cd-pin {
rockchip,pins =
<2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 1ebb0eef42da..5d25a9d04051 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -483,9 +483,9 @@ tsadc: tsadc@ff280000 {
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1145,7 +1145,7 @@ spi2_tx: spi2-tx {
};
tsadc {
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index 20b5599f5e78..6db18808b9c5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -589,11 +589,11 @@ pcie_3g_drv: pcie-3g-drv {
};
pmic {
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
index 4373ed732af7..60cd1c18cd4e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
@@ -499,7 +499,7 @@ &i2s0_8ch_bus {
};
/* there is no external pull up, so need to set this pin pull up */
-&sdmmc_cd_gpio {
+&sdmmc_cd_pin {
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 2f3997740068..32dcaf210085 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -516,7 +516,7 @@ &sdmmc {
* configured as SDMMC and not JTAG.
*/
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin
&sdmmc_bus4>;
bus-width = <4>;
@@ -767,7 +767,7 @@ sdmmc_cd: sdmmc-cd {
};
/* This is where we actually hook up CD; has external pull */
- sdmmc_cd_gpio: sdmmc-cd-gpio {
+ sdmmc_cd_pin: sdmmc-cd-pin {
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
index bf87fa32d3b1..341d074ed996 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
@@ -205,7 +205,7 @@ vdd_cpu_b: syr827@40 {
compatible = "silergy,syr827";
reg = <0x40>;
regulator-compatible = "fan53555-reg";
- pinctrl-0 = <&vsel1_gpio>;
+ pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -223,7 +223,7 @@ vdd_gpu: syr828@41 {
compatible = "silergy,syr828";
reg = <0x41>;
regulator-compatible = "fan53555-reg";
- pinctrl-0 = <&vsel2_gpio>;
+ pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -521,12 +521,12 @@ pmic_int_l: pmic-int-l {
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins =
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins =
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
index 73be38a53796..1fa80ac15464 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
@@ -341,7 +341,7 @@ vdd_cpu_b: regulator@40 {
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel1_gpio>;
+ pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -360,7 +360,7 @@ vdd_gpu: regulator@41 {
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel2_gpio>;
+ pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -447,11 +447,11 @@ pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
index 8f5b2df01560..06d48338c836 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
@@ -40,7 +40,7 @@ edp_panel: edp-panel {
backlight = <&backlight>;
enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&panel_en_gpio>;
+ pinctrl-0 = <&panel_en_pin>;
power-supply = <&vcc3v3_panel>;
ports {
@@ -67,7 +67,7 @@ panel_in_edp: endpoint@0 {
gpio-key-lid {
compatible = "gpio-keys";
pinctrl-names = "default";
- pinctrl-0 = <&lidbtn_gpio>;
+ pinctrl-0 = <&lidbtn_pin>;
lid {
debounce-interval = <20>;
@@ -83,7 +83,7 @@ lid {
gpio-key-power {
compatible = "gpio-keys";
pinctrl-names = "default";
- pinctrl-0 = <&pwrbtn_gpio>;
+ pinctrl-0 = <&pwrbtn_pin>;
power {
debounce-interval = <20>;
@@ -124,7 +124,7 @@ sdio_pwrseq: sdio-pwrseq {
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
- pinctrl-0 = <&wifi_enable_h_gpio>;
+ pinctrl-0 = <&wifi_enable_h_pin>;
post-power-on-delay-ms = <100>;
power-off-delay-us = <500000>;
@@ -136,7 +136,7 @@ sdio_pwrseq: sdio-pwrseq {
es8316-sound {
compatible = "simple-audio-card";
pinctrl-names = "default";
- pinctrl-0 = <&hp_det_gpio>;
+ pinctrl-0 = <&hp_det_pin>;
simple-audio-card,name = "rockchip,es8316-codec";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
@@ -220,7 +220,7 @@ vcc5v0_usb: pa_5v: vcc5v0-usb-regulator {
enable-active-high;
gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&pwr_5v_gpio>;
+ pinctrl-0 = <&pwr_5v_pin>;
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-min-microvolt = <5000000>;
@@ -277,7 +277,7 @@ vcc3v0_sd: vcc3v0-sd {
enable-active-high;
gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_pwr_h_gpio>;
+ pinctrl-0 = <&sdmmc0_pwr_h_pin>;
regulator-name = "vcc3v0_sd";
regulator-always-on;
regulator-min-microvolt = <3000000>;
@@ -295,7 +295,7 @@ vcc3v3_panel: vcc3v3-panel {
enable-active-high;
gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&lcdvcc_en_gpio>;
+ pinctrl-0 = <&lcdvcc_en_pin>;
regulator-name = "vcc3v3_panel";
regulator-always-on;
regulator-min-microvolt = <3300000>;
@@ -324,7 +324,7 @@ vcc5v0_otg: vcc5v0-otg {
enable-active-high;
gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en_gpio>;
+ pinctrl-0 = <&vcc5v0_host_en_pin>;
regulator-name = "vcc5v0_otg";
regulator-always-on;
regulator-min-microvolt = <5000000>;
@@ -343,7 +343,7 @@ vbus_5vout: vbus_typec: vbus-5vout {
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_typec0_en_gpio>;
+ pinctrl-0 = <&vcc5v0_typec0_en_pin>;
regulator-name = "vbus_5vout";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -375,7 +375,7 @@ mains_charger: dc-charger {
/* Also triggered by USB charger */
pinctrl-names = "default";
- pinctrl-0 = <&dc_det_gpio>;
+ pinctrl-0 = <&dc_det_pin>;
};
};
@@ -454,7 +454,7 @@ rk808: pmic@1b {
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l_gpio>;
+ pinctrl-0 = <&pmic_int_l_pin>;
rockchip,system-power-controller;
wakeup-source;
@@ -634,7 +634,7 @@ vdd_cpu_b: regulator@40 {
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel1_gpio>;
+ pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-always-on;
regulator-boot-on;
@@ -653,7 +653,7 @@ vdd_gpu: regulator@41 {
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel2_gpio>;
+ pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
@@ -700,7 +700,7 @@ fusb0: fusb30x@22 {
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&fusb0_int_gpio>;
+ pinctrl-0 = <&fusb0_int_pin>;
vbus-supply = <&vbus_typec>;
connector {
@@ -770,7 +770,7 @@ cw2015@62 {
&i2s1 {
pinctrl-names = "default";
- pinctrl-0 = <&i2s_8ch_mclk_gpio>, <&i2s1_2ch_bus>;
+ pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>;
rockchip,capture-channels = <8>;
rockchip,playback-channels = <8>;
status = "okay";
@@ -802,49 +802,49 @@ &pcie0 {
&pinctrl {
buttons {
- pwrbtn_gpio: pwrbtn-gpio {
+ pwrbtn_pin: pwrbtn-pin {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
- lidbtn_gpio: lidbtn-gpio {
+ lidbtn_pin: lidbtn-pin {
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
dc-charger {
- dc_det_gpio: dc-det-gpio {
+ dc_det_pin: dc-det-pin {
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
es8316 {
- hp_det_gpio: hp-det-gpio {
+ hp_det_pin: hp-det-pin {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
fusb302x {
- fusb0_int_gpio: fusb0-int-gpio {
+ fusb0_int_pin: fusb0-int-pin {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
i2s1 {
- i2s_8ch_mclk_gpio: i2s-8ch-mclk-gpio {
+ i2s_8ch_mclk_pin: i2s-8ch-mclk-pin {
rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
};
};
lcd-panel {
- lcdvcc_en_gpio: lcdvcc-en-gpio {
+ lcdvcc_en_pin: lcdvcc-en-pin {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
- panel_en_gpio: panel-en-gpio {
+ panel_en_pin: panel-en-pin {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
- lcd_panel_reset_gpio: lcd-panel-reset-gpio {
+ lcd_panel_reset_pin: lcd-panel-reset-pin {
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
@@ -860,58 +860,58 @@ slp_led_pin: slp-led-pin {
};
pmic {
- pmic_int_l_gpio: pmic-int-l-gpio {
+ pmic_int_l_pin: pmic-int-l-pin {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdcard {
- sdmmc0_pwr_h_gpio: sdmmc0-pwr-h-gpio {
+ sdmmc0_pwr_h_pin: sdmmc0-pwr-h-pin {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
- wifi_enable_h_gpio: wifi-enable-h-gpio {
+ wifi_enable_h_pin: wifi-enable-h-pin {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
- vcc5v0_typec0_en_gpio: vcc5v0-typec0-en-gpio {
+ vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
- pwr_5v_gpio: pwr-5v-gpio {
+ pwr_5v_pin: pwr-5v-pin {
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
- vcc5v0_host_en_gpio: vcc5v0-host-en-gpio {
+ vcc5v0_host_en_pin: vcc5v0-host-en-pin {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
- bt_wake_gpio: bt-wake-gpio {
+ bt_wake_pin: bt-wake-pin {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
- bt_host_wake_gpio: bt-host-wake-gpio {
+ bt_host_wake_pin: bt-host-wake-pin {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
- bt_reset_gpio: bt-reset-gpio {
+ bt_reset_pin: bt-reset-pin {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -1059,7 +1059,7 @@ bluetooth {
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake_gpio &bt_wake_gpio &bt_reset_gpio>;
+ pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
vbat-supply = <&wifi_bat>;
vddio-supply = <&vcc_wl>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
index 9f225e9c3d54..59b89d6ccdef 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
@@ -456,7 +456,7 @@ vdd_cpu_b: regulator@40 {
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel1_gpio>;
+ pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -475,7 +475,7 @@ vdd_gpu: regulator@41 {
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel2_gpio>;
+ pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -609,11 +609,11 @@ yellow_led_gpio: yellow_led-gpio {
};
pmic {
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
index 3923ec01ef66..60f98a3e19d8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
@@ -390,7 +390,7 @@ vdd_cpu_b: regulator@40 {
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel1_gpio>;
+ pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -409,7 +409,7 @@ vdd_gpu: regulator@41 {
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel2_gpio>;
+ pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -532,11 +532,11 @@ pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
index ba7c75c9f2a1..5e3ac589bc54 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
@@ -470,12 +470,12 @@ pmic_int_l: pmic-int-l {
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins =
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins =
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 3456ee97c288..c84cad16118a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -445,7 +445,7 @@ vdd_cpu_b: regulator@40 {
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel1_gpio>;
+ pinctrl-0 = <&vsel1_pin>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -464,7 +464,7 @@ vdd_gpu: regulator@41 {
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&vsel2_gpio>;
+ pinctrl-0 = <&vsel2_pin>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -612,11 +612,11 @@ pmic_int_l: pmic-int-l {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
index 1bc1579674e5..701a567d7638 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
@@ -481,11 +481,11 @@ pmic_int_l: pmic-int-l {
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
- vsel1_gpio: vsel1-gpio {
+ vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 2581e9cc7a1d..781b5c2cdb4d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -845,9 +845,9 @@ tsadc: tsadc@ff260000 {
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <95000>;
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
@@ -2485,7 +2485,7 @@ test_clkout2: test-clkout2 {
};
tsadc {
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
From b73a18f9f69f893cb7ae0155770d4eac8cc9874f Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx6244@gmail.com>
Date: Fri, 22 May 2020 17:46:57 +0200
Subject: [PATCH] arm64: dts: rockchip: rename and label gpio-led subnodes part
2
Current dts files with 'gpio-led' nodes were manually verified.
In order to automate this process leds-gpio.txt
has been converted to yaml. With this conversion a check
for pattern properties was added. In part 2 rename and label
gpio-led subnodes that passed the regex, but still don't have
the preferred form. Any pin subnode that ends with '-gpio'
in the pinctrl node generates a warning.
Fix with help of the following rules:
1: Add nodename in the preferred form.
2: Always add a label that ends with '_led' to prevent conflicts
with other labels such as 'power' and 'mmc'
3: If leds need pinctrl add a label that ends with '_led_pin'
also to prevent conflicts with other labels.
patternProperties:
# The first form is preferred, but fall back to just 'led'
# anywhere in the node name to at least catch some child nodes.
"(^led-[0-9a-f]$|led)":
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/leds/
leds-gpio.yaml
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/
schemas/gpio/gpio.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200522154657.9472-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 6dd5e12c0b9bba40b3947ac1a9fd2f992585b5c6)
---
.../arm64/boot/dts/rockchip/rk3368-lion-haikou.dts | 6 +++---
arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 8 ++++----
.../boot/dts/rockchip/rk3399-khadas-edge.dtsi | 10 +++++-----
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 6 +++---
.../arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 6 +++---
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 6 +++---
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 14 +++++++-------
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 10 +++++-----
8 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
index dbd2caba322f..7fcb1eacea8a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
@@ -25,9 +25,9 @@ eeprom: eeprom@50 {
};
leds {
- pinctrl-0 = <&led_pins_module>, <&led_sd_haikou>;
+ pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
- sd-card-led {
+ sd_card_led: led-3 {
label = "sd_card_led";
gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
@@ -118,7 +118,7 @@ haikou_pin_hog: haikou-pin-hog {
};
leds {
- led_sd_haikou: led-sd-gpio {
+ sd_card_led_pin: sd-card-led-pin {
rockchip,pins =
<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
index 216aafd90e7f..24d28be4736c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
@@ -76,16 +76,16 @@ i2c@1 {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&led_pins_module>;
+ pinctrl-0 = <&module_led_pins>;
- module_led1 {
+ module_led1: led-1 {
label = "module_led1";
gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
panic-indicator;
};
- module_led2 {
+ module_led2: led-2 {
label = "module_led2";
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
default-state = "off";
@@ -270,7 +270,7 @@ &i2c2 {
&pinctrl {
leds {
- led_pins_module: led-module-gpio {
+ module_led_pins: module-led-pins {
rockchip,pins =
<2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
index e87a04477440..e36837c04dc7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
@@ -141,15 +141,15 @@ power {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>;
+ pinctrl-0 = <&sys_led_pin>, <&user_led_pin>;
- sys-led {
+ sys_led: led-0 {
label = "sys_led";
linux,default-trigger = "heartbeat";
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
};
- user-led {
+ user_led: led-1 {
label = "user_led";
default-state = "off";
gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
@@ -586,11 +586,11 @@ pwrbtn: pwrbtn {
};
leds {
- sys_led_gpio: sys_led-gpio {
+ sys_led_pin: sys-led-pin {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
- user_led_gpio: user_led-gpio {
+ user_led_pin: user-led-pin {
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index 1d246c2caa3c..76a8b40a93c6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -117,9 +117,9 @@ power {
leds: gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&leds_gpio>;
+ pinctrl-0 = <&status_led_pin>;
- status {
+ status_led: led-0 {
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
label = "status_led";
linux,default-trigger = "heartbeat";
@@ -520,7 +520,7 @@ fusb0_int: fusb0-int {
};
gpio-leds {
- leds_gpio: leds-gpio {
+ status_led_pin: status-led-pin {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
index d80d6b726820..a8d363568fd6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
@@ -15,9 +15,9 @@ chosen {
};
leds {
- pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>;
+ pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
- sd-card-led {
+ sd_card_led: led-1 {
label = "sd_card_led";
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
@@ -179,7 +179,7 @@ haikou_pin_hog: haikou-pin-hog {
};
leds {
- led_sd_haikou: led-sd-gpio {
+ sd_card_led_pin: sd-card-led-pin {
rockchip,pins =
<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
index 72c06abd27ea..4660416c8f38 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
@@ -11,9 +11,9 @@ / {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&led_pin_module>;
+ pinctrl-0 = <&module_led_pin>;
- module-led {
+ module_led: led-0 {
label = "module_led";
gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -450,7 +450,7 @@ i2c8_xfer_a: i2c8-xfer {
};
leds {
- led_pin_module: led-module-gpio {
+ module_led_pin: module-led-pin {
rockchip,pins =
<2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
index 59b89d6ccdef..b85ec31cd283 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
@@ -61,23 +61,23 @@ power {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>, <&yellow_led_gpio>;
+ pinctrl-0 = <&work_led_pin>, <&diy_led_pin>, <&yellow_led_pin>;
- work-led {
+ work_led: led-0 {
label = "green:work";
gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
- diy-led {
+ diy_led: led-1 {
label = "red:diy";
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc1";
};
- yellow-led {
+ yellow_led: led-2 {
label = "yellow:yellow-led";
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
default-state = "off";
@@ -595,15 +595,15 @@ lcd_panel_reset: lcd-panel-reset {
};
leds {
- diy_led_gpio: diy_led-gpio {
+ diy_led_pin: diy-led-pin {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
- work_led_gpio: work_led-gpio {
+ work_led_pin: work-led-pin {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
- yellow_led_gpio: yellow_led-gpio {
+ yellow_led_pin: yellow-led-pin {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index c84cad16118a..6e553ff47534 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -39,15 +39,15 @@ power {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
+ pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
- work-led {
+ work_led: led-0 {
label = "work";
default-state = "on";
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
};
- diy-led {
+ diy_led: led-1 {
label = "diy";
default-state = "off";
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
@@ -588,11 +588,11 @@ fusb0_int: fusb0-int {
};
leds {
- work_led_gpio: work_led-gpio {
+ work_led_pin: work-led-pin {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
- diy_led_gpio: diy_led-gpio {
+ diy_led_pin: diy-led-pin {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
From c40071fd1c70da63fdd7cc308114b34623d7eb91 Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx6244@gmail.com>
Date: Sun, 24 May 2020 18:06:35 +0200
Subject: [PATCH] ARM: dts: rockchip: rename label and nodename pinctrl
subnodes that end with gpio
A test with the command below gives for example this error:
arch/arm/boot/dts/rk3288-tinker.dt.yaml: tsadc: otp-gpio:
{'phandle': [[54]], 'rockchip,pins': [[0, 10, 0, 118]]}
is not of type 'array'
'gpio' is a sort of reserved nodename and should not be used
for pinctrl in combination with 'rockchip,pins', so change
nodes that end with 'gpio' to end with 'pin' or 'pins'.
make ARCH=arm dtbs_check
DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/
dtschema/schemas/gpio/gpio.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200524160636.16547-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit fff987e7328951f7d6fb2d0545de8635ceafa89f)
---
arch/arm/boot/dts/rk322x.dtsi | 6 +++---
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 2 +-
arch/arm/boot/dts/rk3288-veyron-jerry.dts | 2 +-
arch/arm/boot/dts/rk3288-veyron-mighty.dts | 6 +++---
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 +-
arch/arm/boot/dts/rk3288-veyron-pinky.dts | 6 +++---
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 2 +-
arch/arm/boot/dts/rk3288-veyron-speedy.dts | 2 +-
arch/arm/boot/dts/rk3288.dtsi | 6 +++---
arch/arm/boot/dts/rv1108.dtsi | 12 ++++++------
10 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index b0fd92befdeb..3236abb0aba9 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -520,9 +520,9 @@ tsadc: tsadc@11150000 {
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <0>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1111,7 +1111,7 @@ spdif_tx: spdif-tx {
};
tsadc {
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
index 171ba6185b6d..8efba9deae3c 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -47,7 +47,7 @@ regulator-state-mem {
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
index 66f00d28801a..2c916c50dda5 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
@@ -192,7 +192,7 @@ mwifiex: wifi@1 {
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts
index 27fbc07476d2..fa695a88f236 100644
--- a/arch/arm/boot/dts/rk3288-veyron-mighty.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts
@@ -18,8 +18,8 @@ / {
};
&sdmmc {
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
- &sdmmc_wp_gpio &sdmmc_bus4>;
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
+ &sdmmc_wp_pin &sdmmc_bus4>;
wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
/delete-property/ disable-wp;
@@ -27,7 +27,7 @@ &sdmmc {
&pinctrl {
sdmmc {
- sdmmc_wp_gpio: sdmmc-wp-gpio {
+ sdmmc_wp_pin: sdmmc-wp-pin {
rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index 383fad1a88a1..f8b69e0a16a0 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -114,7 +114,7 @@ regulator-state-mem {
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
index 71e6629cc208..4e9fdb0f722d 100644
--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
@@ -105,7 +105,7 @@ emmc_reset: emmc-reset {
};
sdmmc {
- sdmmc_wp_gpio: sdmmc-wp-gpio {
+ sdmmc_wp_pin: sdmmc-wp-pin {
rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
@@ -126,8 +126,8 @@ regulator-state-mem {
&sdmmc {
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
- &sdmmc_wp_gpio &sdmmc_bus4>;
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
+ &sdmmc_wp_pin &sdmmc_bus4>;
wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
index fe950f9863e8..27fb06ce907e 100644
--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
@@ -41,7 +41,7 @@ sdmmc_cd_disabled: sdmmc-cd-disabled {
};
/* This is where we actually hook up CD */
- sdmmc_cd_gpio: sdmmc-cd-gpio {
+ sdmmc_cd_pin: sdmmc-cd-pin {
rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
index e354c61a45e7..4a3ea934d03e 100644
--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
@@ -54,7 +54,7 @@ &rk808 {
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2e1edd85f04a..84d59469035e 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -574,9 +574,9 @@ tsadc: tsadc@ff280000 {
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <1>;
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <95000>;
@@ -1929,7 +1929,7 @@ uart4_rts: uart4-rts {
};
tsadc {
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index f9cfe2c80791..a5d130bd0547 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -351,9 +351,9 @@ tsadc: tsadc@10370000 {
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
rockchip,hw-tshut-temp = <120000>;
@@ -728,7 +728,7 @@ i2c2m1_xfer: i2c2m1-xfer {
<0 RK_PC6 3 &pcfg_pull_none>;
};
- i2c2m1_gpio: i2c2m1-gpio {
+ i2c2m1_pins: i2c2m1-pins {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -740,7 +740,7 @@ i2c2m05v_xfer: i2c2m05v-xfer {
<1 RK_PD4 2 &pcfg_pull_none>;
};
- i2c2m05v_gpio: i2c2m05v-gpio {
+ i2c2m05v_pins: i2c2m05v-pins {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -867,7 +867,7 @@ otp_out: otp-out {
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
};
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -886,7 +886,7 @@ uart0_rts: uart0-rts {
rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
};
- uart0_rts_gpio: uart0-rts-gpio {
+ uart0_rts_pin: uart0-rts-pin {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
From c07b527960a7909caa8adb15247362f2319f1653 Mon Sep 17 00:00:00 2001
From: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
Date: Fri, 12 Jun 2020 13:02:48 -0700
Subject: [PATCH] ARM: dts: rockchip: Add marvell BT irq config
Veyron Jaq and Mighty both use the Marvel 8897 WiFi+BT chip. Add wakeup
and pinctrl block to devicetree so the btmrvl driver can correctly
configure the wakeup interrupt.
Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200612130219.v2.1.I66864be898aa835ccb66b6cd5220d0b082338a81@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 6c2b99a2e7a073575b4ee91abf7d16470991c1f4)
---
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
index 8efba9deae3c..af77ab20586d 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -44,6 +44,21 @@ regulator-state-mem {
};
};
+&sdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ btmrvl: btmrvl@2 {
+ compatible = "marvell,sd8897-bt";
+ reg = <2>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
+ marvell,wakeup-pin = /bits/ 16 <13>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l>;
+ };
+};
+
&sdmmc {
disable-wp;
pinctrl-names = "default";
From f0ee8fdc42d8bb5a2cb126df71302324fb23866b Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Thu, 4 Jun 2020 09:36:38 +0800
Subject: [PATCH] dmaengine: pl330: Make sure the debug is idle before doing
DMAGO
According to the datasheet of pl330:
Example 2-1 Using DMAGO with the debug instruction registers
1. Create a program for the DMA channel
2. Store the program in a region of system memory
3. Poll the DBGSTATUS Register to ensure that the debug is idle
4. Write to the DBGINST0 Register
5. Write to the DBGINST1 Register
6. Write zero to the DBGCMD Register
so, we should make sure the debug is idle before step 4/5/6, not
only step 6. if not, there maybe a risk that fail to write DBGINST0/1.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1591234598-78919-1-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit d12ea5591eddf625b7707c018b72e46e8674c3c2)
---
drivers/dma/pl330.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 88b884cbb7c1..6a158eef6b8a 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -885,6 +885,12 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd,
void __iomem *regs = thrd->dmac->base;
u32 val;
+ /* If timed out due to halted state-machine */
+ if (_until_dmac_idle(thrd)) {
+ dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
+ return;
+ }
+
val = (insn[0] << 16) | (insn[1] << 24);
if (!as_manager) {
val |= (1 << 0);
@@ -895,12 +901,6 @@ static inline void _execute_DBGINSN(struct pl330_thread *thrd,
val = le32_to_cpu(*((__le32 *)&insn[2]));
writel(val, regs + DBGINST1);
- /* If timed out due to halted state-machine */
- if (_until_dmac_idle(thrd)) {
- dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
- return;
- }
-
/* Get going */
writel(0, regs + DBGCMD);
}
From e5214dd97994bfdb32dcae94e03f18a794c43947 Mon Sep 17 00:00:00 2001
From: Shunqian Zheng <zhengsq@rock-chips.com>
Date: Fri, 3 Apr 2020 13:15:37 -0300
Subject: [PATCH] arm64: dts: rockchip: add rx0 mipi-phy for rk3399
Designware MIPI D-PHY, used for ISP0 in rk3399.
Verified with:
make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Link: https://lore.kernel.org/r/20200403161538.1375908-9-helen.koike@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit e4bfde13e323f9ee5f2f38aa5cac0676dd656f8e)
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 781b5c2cdb4d..f2ef0d8ba54b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1397,6 +1397,17 @@ io_domains: io-domains {
status = "disabled";
};
+ mipi_dphy_rx0: mipi-dphy-rx0 {
+ compatible = "rockchip,rk3399-mipi-dphy-rx0";
+ clocks = <&cru SCLK_MIPIDPHY_REF>,
+ <&cru SCLK_DPHY_RX0_CFG>,
+ <&cru PCLK_VIO_GRF>;
+ clock-names = "dphy-ref", "dphy-cfg", "grf";
+ power-domains = <&power RK3399_PD_VIO>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
From d2266424a494804c6709ea8231fc44e1ca376138 Mon Sep 17 00:00:00 2001
From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Date: Tue, 7 Jul 2020 14:06:10 -0500
Subject: [PATCH] ASoC: codecs: es8316: fix 'defined but not used' warning
Fix W=1 warning
sound/soc/codecs/es8316.c:842:36: warning: 'es8316_acpi_match' defined
but not used [-Wunused-const-variable=]
842 | static const struct acpi_device_id es8316_acpi_match[] = {
| ^~~~~~~~~~~~~~~~~
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20200707190612.97799-12-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 07ac670981fc5932ca3799ce7d96431d80afce0e)
---
sound/soc/codecs/es8316.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c
index 36eef1fb3d18..70af35c5f727 100644
--- a/sound/soc/codecs/es8316.c
+++ b/sound/soc/codecs/es8316.c
@@ -839,11 +839,13 @@ static const struct of_device_id es8316_of_match[] = {
};
MODULE_DEVICE_TABLE(of, es8316_of_match);
+#ifdef CONFIG_ACPI
static const struct acpi_device_id es8316_acpi_match[] = {
{"ESSX8316", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, es8316_acpi_match);
+#endif
static struct i2c_driver es8316_i2c_driver = {
.driver = {
From 2a38a809f8b033a5ddae29b81fb1209a897689f5 Mon Sep 17 00:00:00 2001
From: Vinod Koul <vkoul@kernel.org>
Date: Wed, 8 Jul 2020 18:58:07 +0530
Subject: [PATCH] phy: rockchip-typec: use correct format for structure
description
We get warning with W=1 build:
drivers/phy/rockchip/phy-rockchip-typec.c:360: warning: cannot
understand function prototype: 'struct rockchip_usb3phy_port_cfg '
The 'struct rockchip_usb3phy_port_cfg ' is commented properly but uses
wrong format, so fix that up
Link: https://lore.kernel.org/r/20200708132809.265967-4-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit 72fbf95f36218ec2a901e0eb7c3aa0bea6f1f396)
---
drivers/phy/rockchip/phy-rockchip-typec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index 24563160197f..70a31251b202 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -347,7 +347,7 @@ struct usb3phy_reg {
};
/**
- * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
+ * struct rockchip_usb3phy_port_cfg - usb3-phy port configuration.
* @reg: the base address for usb3-phy config.
* @typec_conn_dir: the register of type-c connector direction.
* @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
From 4210b54dbec5ef3259494989feab48ffde364bb2 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Mon, 13 Jul 2020 18:26:00 +0800
Subject: [PATCH] ASoC: rockchip: spdif: Handle clk by pm runtime
This patch handle the clk by pm runtime mechanism to simplify
the clk management.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1594635960-67855-1-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit f50d67f9eff62f8078fe6e98ede3f4fb1defc361)
---
sound/soc/rockchip/rockchip_spdif.c | 59 +++++++++--------------------
1 file changed, 17 insertions(+), 42 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c
index 6635145a26c4..674810851fbc 100644
--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
@@ -306,44 +306,22 @@ static int rk_spdif_probe(struct platform_device *pdev)
return -ENOMEM;
spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
- if (IS_ERR(spdif->hclk)) {
- dev_err(&pdev->dev, "Can't retrieve rk_spdif bus clock\n");
+ if (IS_ERR(spdif->hclk))
return PTR_ERR(spdif->hclk);
- }
- ret = clk_prepare_enable(spdif->hclk);
- if (ret) {
- dev_err(spdif->dev, "hclock enable failed %d\n", ret);
- return ret;
- }
spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
- if (IS_ERR(spdif->mclk)) {
- dev_err(&pdev->dev, "Can't retrieve rk_spdif master clock\n");
- ret = PTR_ERR(spdif->mclk);
- goto err_disable_hclk;
- }
-
- ret = clk_prepare_enable(spdif->mclk);
- if (ret) {
- dev_err(spdif->dev, "clock enable failed %d\n", ret);
- goto err_disable_clocks;
- }
+ if (IS_ERR(spdif->mclk))
+ return PTR_ERR(spdif->mclk);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(regs)) {
- ret = PTR_ERR(regs);
- goto err_disable_clocks;
- }
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
&rk_spdif_regmap_config);
- if (IS_ERR(spdif->regmap)) {
- dev_err(&pdev->dev,
- "Failed to initialise managed register map\n");
- ret = PTR_ERR(spdif->regmap);
- goto err_disable_clocks;
- }
+ if (IS_ERR(spdif->regmap))
+ return PTR_ERR(spdif->regmap);
spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -352,47 +330,44 @@ static int rk_spdif_probe(struct platform_device *pdev)
spdif->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, spdif);
- pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
- pm_request_idle(&pdev->dev);
+ if (!pm_runtime_enabled(&pdev->dev)) {
+ ret = rk_spdif_runtime_resume(&pdev->dev);
+ if (ret)
+ goto err_pm_runtime;
+ }
ret = devm_snd_soc_register_component(&pdev->dev,
&rk_spdif_component,
&rk_spdif_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI\n");
- goto err_pm_runtime;
+ goto err_pm_suspend;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM\n");
- goto err_pm_runtime;
+ goto err_pm_suspend;
}
return 0;
+err_pm_suspend:
+ if (!pm_runtime_status_suspended(&pdev->dev))
+ rk_spdif_runtime_suspend(&pdev->dev);
err_pm_runtime:
pm_runtime_disable(&pdev->dev);
-err_disable_clocks:
- clk_disable_unprepare(spdif->mclk);
-err_disable_hclk:
- clk_disable_unprepare(spdif->hclk);
return ret;
}
static int rk_spdif_remove(struct platform_device *pdev)
{
- struct rk_spdif_dev *spdif = dev_get_drvdata(&pdev->dev);
-
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
rk_spdif_runtime_suspend(&pdev->dev);
- clk_disable_unprepare(spdif->mclk);
- clk_disable_unprepare(spdif->hclk);
-
return 0;
}
From 6af0776af231629c2331f81faa2fdb311cf3ed44 Mon Sep 17 00:00:00 2001
From: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Date: Tue, 14 Jul 2020 16:32:47 +0900
Subject: [PATCH] ASoC: convert rk3328 codec binding to yaml
This patch converts Rockchip rk3328 audio codec binding to DT schema.
And adds description about "mclk" clock and fixes some errors in
original example.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200714073247.172859-1-katsuhiro@katsuster.net
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 3f6597ad2f9ed8ed89dbd2a9ec0b0c892774f9d2)
---
.../bindings/sound/rockchip,rk3328-codec.txt | 28 --------
.../bindings/sound/rockchip,rk3328-codec.yaml | 69 +++++++++++++++++++
2 files changed, 69 insertions(+), 28 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt
create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.yaml
diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt
deleted file mode 100644
index 1ecd75d2032a..000000000000
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Rockchip Rk3328 internal codec
-
-Required properties:
-
-- compatible: "rockchip,rk3328-codec"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- rockchip,grf: the phandle of the syscon node for GRF register.
-- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
-- clock-names: should be "pclk".
-- spk-depop-time-ms: speak depop time msec.
-
-Optional properties:
-
-- mute-gpios: GPIO specifier for external line driver control (typically the
- dedicated GPIO_MUTE pin)
-
-Example for rk3328 internal codec:
-
-codec: codec@ff410000 {
- compatible = "rockchip,rk3328-codec";
- reg = <0x0 0xff410000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- clocks = <&cru PCLK_ACODEC>;
- clock-names = "pclk";
- mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
- spk-depop-time-ms = 100;
-};
diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.yaml b/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.yaml
new file mode 100644
index 000000000000..5b85ad5e4834
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3328-codec.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/rockchip,rk3328-codec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip rk3328 internal codec
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ const: rockchip,rk3328-codec
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: clock for audio codec
+ - description: clock for I2S master clock
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: mclk
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle of the syscon node for the GRF register.
+
+ spk-depop-time-ms:
+ default: 200
+ description:
+ Speaker depop time in msec.
+
+ mute-gpios:
+ maxItems: 1
+ description:
+ GPIO specifier for external line driver control (typically the
+ dedicated GPIO_MUTE pin)
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - rockchip,grf
+ - "#sound-dai-cells"
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/rk3328-cru.h>
+ codec: codec@ff410000 {
+ compatible = "rockchip,rk3328-codec";
+ reg = <0xff410000 0x1000>;
+ clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
+ clock-names = "pclk", "mclk";
+ rockchip,grf = <&grf>;
+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
+ spk-depop-time-ms = <100>;
+ #sound-dai-cells = <0>;
+ };
From 6917bb6287536dbdd26511d0ba6e6b82bc0f5d86 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Mon, 29 Jun 2020 22:05:42 +0800
Subject: [PATCH] dmaengine: pl330: Remove the burst limit for quirk
'NO-FLUSHP'
There is no reason to limit the performance on the 'NO-FLUSHP' SoCs,
because 'FLUSHP' instruction is broken on these platforms, so remove
the limit to improve the efficiency.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1593439555-68130-2-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit 05611a93b8ffa3fe7d2eb43dd6c11e37ead5908a)
---
drivers/dma/pl330.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 6a158eef6b8a..7686292bc1db 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -1183,9 +1183,6 @@ static inline int _ldst_peripheral(struct pl330_dmac *pl330,
{
int off = 0;
- if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
- cond = BURST;
-
/*
* do FLUSHP at beginning to clear any stale dma requests before the
* first WFP.
@@ -2221,9 +2218,7 @@ static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
static int fixup_burst_len(int max_burst_len, int quirks)
{
- if (quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
- return 1;
- else if (max_burst_len > PL330_MAX_BURST)
+ if (max_burst_len > PL330_MAX_BURST)
return PL330_MAX_BURST;
else if (max_burst_len < 1)
return 1;
@@ -3128,8 +3123,7 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
- pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
- 1 : PL330_MAX_BURST);
+ pd->max_burst = PL330_MAX_BURST;
ret = dma_async_device_register(pd);
if (ret) {
From cb00fa158b947abf47ce2f256139a849b3bc8f2e Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Mon, 29 Jun 2020 22:05:43 +0800
Subject: [PATCH] dmaengine: pl330: Improve transfer efficiency for the dregs
Only the unaligned burst transfers have the dregs.
so, still use BURST transfer with a reduced size
for better performance.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1593439555-68130-3-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit 3e7f0bd872087bf4653eeee9a83050f91baae907)
---
drivers/dma/pl330.c | 32 +++++++++++++++++++++-----------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 7686292bc1db..f1f0176c6c05 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -1228,8 +1228,9 @@ static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
}
/*
- * transfer dregs with single transfers to peripheral, or a reduced size burst
- * for mem-to-mem.
+ * only the unaligned burst transfers have the dregs.
+ * so, still transfer dregs with a reduced size burst
+ * for mem-to-mem, mem-to-dev or dev-to-mem.
*/
static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
const struct _xfer_spec *pxs, int transfer_length)
@@ -1240,22 +1241,31 @@ static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
if (transfer_length == 0)
return off;
+ /*
+ * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
+ * BRST_SIZE(ccr)
+ * the dregs len must be smaller than burst len,
+ * so, for higher efficiency, we can modify CCR
+ * to use a reduced size burst len for the dregs.
+ */
+ dregs_ccr = pxs->ccr;
+ dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
+ (0xf << CC_DSTBRSTLEN_SHFT));
+ dregs_ccr |= (((transfer_length - 1) & 0xf) <<
+ CC_SRCBRSTLEN_SHFT);
+ dregs_ccr |= (((transfer_length - 1) & 0xf) <<
+ CC_DSTBRSTLEN_SHFT);
+
switch (pxs->desc->rqtype) {
case DMA_MEM_TO_DEV:
/* fall through */
case DMA_DEV_TO_MEM:
- off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs,
- transfer_length, SINGLE);
+ off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
+ off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
+ BURST);
break;
case DMA_MEM_TO_MEM:
- dregs_ccr = pxs->ccr;
- dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
- (0xf << CC_DSTBRSTLEN_SHFT));
- dregs_ccr |= (((transfer_length - 1) & 0xf) <<
- CC_SRCBRSTLEN_SHFT);
- dregs_ccr |= (((transfer_length - 1) & 0xf) <<
- CC_DSTBRSTLEN_SHFT);
off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
break;
From 73de2b83dab82d5b7ad55360f14b1aa35e55eb8f Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Mon, 29 Jun 2020 22:05:45 +0800
Subject: [PATCH] dmaengine: pl330: Add quirk 'arm,pl330-periph-burst'
This patch adds the qurik to use burst transfers only
for pl330 controller, even for request with a length of 1.
Although, the correct way should be: if the peripheral request
length is 1, the peripheral should use SINGLE request, and then
notify the dmac using SINGLE mode by src/dst_maxburst with 1.
For example, on the Rockchip SoCs, all the peripherals can use
SINGLE or BURST request by setting GRF registers. it is possible
that if these peripheral drivers are used only for Rockchip SoCs.
Unfortunately, it's not, such as dw uart, which is used so widely,
and we can't set src/dst_maxburst according to the SoCs' specific
to compatible with all the other SoCs.
So, for convenience, all the peripherals are set as BURST request
by default on the Rockchip SoCs. even for request with a length of 1.
the current pl330 driver will perform SINGLE transfer if the client's
maxburst is 1, which still should be working according to chapter 2.6.6
of datasheet which describe how DMAC performs SINGLE transfers for
a BURST request. Unfortunately, it's broken on the Rockchip SoCs,
which support only matching transfers, such as BURST transfer for
BURST request, SINGLE transfer for SINGLE request.
Finally, we add the quirk to specify pl330 to use burst transfers only.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1593439555-68130-5-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit 5fb9e3a3423313fe6169d5069e471bfdab6e0b79)
---
drivers/dma/pl330.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index f1f0176c6c05..3be8d462eab4 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -33,7 +33,8 @@
#define PL330_MAX_PERI 32
#define PL330_MAX_BURST 16
-#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
+#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
+#define PL330_QUIRK_PERIPH_BURST BIT(1)
enum pl330_cachectrl {
CCTRL0, /* Noncacheable and nonbufferable */
@@ -509,6 +510,10 @@ static struct pl330_of_quirks {
{
.quirk = "arm,pl330-broken-no-flushp",
.id = PL330_QUIRK_BROKEN_NO_FLUSHP,
+ },
+ {
+ .quirk = "arm,pl330-periph-burst",
+ .id = PL330_QUIRK_PERIPH_BURST,
}
};
@@ -1206,6 +1211,9 @@ static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
int off = 0;
enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
+ if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
+ cond = BURST;
+
switch (pxs->desc->rqtype) {
case DMA_MEM_TO_DEV:
/* fall through */
From e02c5f202e532c3107f055ff4938852675c9effd Mon Sep 17 00:00:00 2001
From: Lee Jones <lee.jones@linaro.org>
Date: Tue, 14 Jul 2020 12:15:34 +0100
Subject: [PATCH] dmaengine: pl330: Demote obvious misuse of kerneldoc to
standard comment block
No 'struct' title is provided. Nor are any attribute descriptions.
Fixes the following W=1 kernel build warning(s):
drivers/dma/pl330.c:295: warning: cannot understand function prototype: 'struct pl330_reqcfg '
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Jaswinder Singh <jassi.brar@samsung.com>
Link: https://lore.kernel.org/r/20200714111546.1755231-6-lee.jones@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit f9e036df575d8efce6fd469acd9df3148c2adf6e)
---
drivers/dma/pl330.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 3be8d462eab4..2c508ee672b9 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -285,7 +285,7 @@ struct pl330_config {
u32 irq_ns;
};
-/**
+/*
* Request Configuration.
* The PL330 core does not modify this and uses the last
* working configuration if the request doesn't provide any.
From 90e0dc93ec0461e912927d1667f31be40a277954 Mon Sep 17 00:00:00 2001
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Date: Thu, 9 Jul 2020 10:55:36 +0900
Subject: [PATCH] ASoC: hdmi-codec: return -ENOTSUPP for digital_mute
snd_soc_dai_digital_mute() will return -ENOTSUPP if driver doesn't
support mute.
In hdmi-codec case, hdmi_codec_digital_mute() will be used for it,
and each driver has .digital_mute() callback.
hdmi_codec_digital_mute() want to return -ENOTSUPP to follow it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87fta1xxjc.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit e07e49c0d1e3693facf588142c4cbde45904b3f8)
---
sound/soc/codecs/hdmi-codec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
index f005751da2cc..926ab447a96b 100644
--- a/sound/soc/codecs/hdmi-codec.c
+++ b/sound/soc/codecs/hdmi-codec.c
@@ -566,7 +566,7 @@ static int hdmi_codec_digital_mute(struct snd_soc_dai *dai, int mute)
return hcp->hcd.ops->digital_mute(dai->dev->parent,
hcp->hcd.data, mute);
- return 0;
+ return -ENOTSUPP;
}
static const struct snd_soc_dai_ops hdmi_codec_i2s_dai_ops = {
From f7c70c0be79698095f473dc90a266d98a4a5d12d Mon Sep 17 00:00:00 2001
From: Johan Jonker <jbx6244@gmail.com>
Date: Wed, 15 Jul 2020 09:09:54 +0200
Subject: [PATCH] arm64: dts: rockchip: remove bus-width from mmc nodes in px30
dts files
'bus-width' has been added to px30.dtsi mmc nodes, so now it can be
removed from the dts files that include it.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200715070954.1992-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit e7e46a1f6b755248058db531b1cff3b0cc580650)
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 3 ---
arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts | 1 -
2 files changed, 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index 0a680257d9c2..5fe905fae9a8 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -145,7 +145,6 @@ &dsi_dphy {
};
&emmc {
- bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
@@ -499,7 +498,6 @@ &saradc {
};
&sdmmc {
- bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <800>;
@@ -513,7 +511,6 @@ &sdmmc {
};
&sdio {
- bus-width = <4>;
cap-sd-highspeed;
keep-power-in-suspend;
non-removable;
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
index b3a8f936578f..35bd6b904b9c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
@@ -445,7 +445,6 @@ &saradc {
};
&sdmmc {
- bus-width = <4>;
cap-sd-highspeed;
card-detect-delay = <200>;
cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
From 3abee17c54e34c806bacab0a257b88ea3d75ab80 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Mon, 29 Jun 2020 22:12:11 +0800
Subject: [PATCH] arm64: dts: rockchip: Add 'arm,pl330-periph-burst' for dmac
This patch Add the quirk to specify to use burst transfer
for better compatible and higher performance.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1593439935-68540-1-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 505af9184ec0a0222bb883486137fac32731e01d)
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 2 ++
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
5 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index e9bb2b97ae55..2695ea8cda14 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -714,6 +714,7 @@ dmac: dmac@ff240000 {
reg = <0x0 0xff240000 0x0 0x4000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
#dma-cells = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index ba1c71568164..e8b754d415d8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -524,6 +524,7 @@ dmac0: dma-controller@ff2c0000 {
reg = <0x0 0xff2c0000 0x0 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -534,6 +535,7 @@ dmac1: dma-controller@ff2d0000 {
reg = <0x0 0xff2d0000 0x0 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 72e655020560..bbdb19a3e85d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -153,6 +153,7 @@ dmac: dmac@ff1f0000 {
reg = <0x0 0xff1f0000 0x0 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
#dma-cells = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 5d25a9d04051..3746f23dc3df 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -149,6 +149,7 @@ dmac_peri: dma-controller@ff250000 {
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC_PERI>;
clock-names = "apb_pclk";
};
@@ -160,6 +161,7 @@ dmac_bus: dma-controller@ff600000 {
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC_BUS>;
clock-names = "apb_pclk";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index f2ef0d8ba54b..ada724b12f01 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -209,6 +209,7 @@ dmac_bus: dma-controller@ff6d0000 {
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC0_PERILP>;
clock-names = "apb_pclk";
};
@@ -219,6 +220,7 @@ dmac_peri: dma-controller@ff6e0000 {
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC1_PERILP>;
clock-names = "apb_pclk";
};
From 932b4a4d3d1ea833e2ac81c122879e4671ee2429 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Mon, 29 Jun 2020 22:10:57 +0800
Subject: [PATCH] ARM: dts: rockchip: Add 'arm,pl330-periph-burst' for dmac
This patch Add the quirk to specify to use burst transfer
for better compatible and higher performance.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1593439866-68459-1-git-send-email-sugar.zhang@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit fb082df317823463eaf09ac88de19fb3319e4f58)
---
arch/arm/boot/dts/rk3036.dtsi | 1 +
arch/arm/boot/dts/rk322x.dtsi | 1 +
arch/arm/boot/dts/rk3288.dtsi | 3 +++
arch/arm/boot/dts/rk3xxx.dtsi | 3 +++
arch/arm/boot/dts/rv1108.dtsi | 1 +
5 files changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index d9a0c9a29b68..093567022386 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -67,6 +67,7 @@ pdma: pdma@20078000 {
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
};
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 3236abb0aba9..48e6e8d44a1a 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -107,6 +107,7 @@ pdma: pdma@110f0000 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 84d59469035e..9fa11b9f4522 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -167,6 +167,7 @@ dmac_peri: dma-controller@ff250000 {
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
};
@@ -178,6 +179,7 @@ dmac_bus_ns: dma-controller@ff600000 {
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
status = "disabled";
@@ -190,6 +192,7 @@ dmac_bus_s: dma-controller@ffb20000 {
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index d929b60517ab..859a7477909f 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -45,6 +45,7 @@ dmac1_s: dma-controller@20018000 {
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMA1>;
clock-names = "apb_pclk";
};
@@ -56,6 +57,7 @@ dmac1_ns: dma-controller@2001c000 {
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMA1>;
clock-names = "apb_pclk";
status = "disabled";
@@ -68,6 +70,7 @@ dmac2: dma-controller@20078000 {
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMA2>;
clock-names = "apb_pclk";
};
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index a5d130bd0547..a1a08cb9364e 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -97,6 +97,7 @@ pdma: pdma@102a0000 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
From ea1abccee16e018a29011224d0e7b5392d818e70 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Wed, 15 Jul 2020 14:04:12 +0530
Subject: [PATCH] ARM: dts: rockchip: dalang-carrier: Move i2c nodes into SOM
I2C nodes and associated slave devices defined in Carrier board
are specific to rk3399pro vmrac SOM.
So, move them into SOM dtsi.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200715083418.112003-2-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c2f343510d99ab53b46bdfeb184cb48f622e6943)
---
.../dts/rockchip-radxa-dalang-carrier.dtsi | 32 -------------------
.../dts/rockchip/rk3399pro-vmarc-som.dtsi | 29 +++++++++++++++++
2 files changed, 29 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
index df3712aedf8a..176b53b8e41a 100644
--- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -17,29 +17,6 @@ &gmac {
status = "okay";
};
-&i2c1 {
- status = "okay";
- i2c-scl-rising-time-ns = <140>;
- i2c-scl-falling-time-ns = <30>;
-};
-
-&i2c2 {
- status = "okay";
- clock-frequency = <400000>;
-
- hym8563: hym8563@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "hym8563";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- interrupt-parent = <&gpio4>;
- interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
&pwm0 {
status = "okay";
};
@@ -70,12 +47,3 @@ &uart0 {
&uart2 {
status = "okay";
};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins =
- <4 RK_PD6 0 &pcfg_pull_up>;
- };
- };
-};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index 0a516334f15f..e11538171e67 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -297,6 +297,29 @@ regulator-state-mem {
};
};
+&i2c1 {
+ i2c-scl-falling-time-ns = <30>;
+ i2c-scl-rising-time-ns = <140>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PD6 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
&io_domains {
status = "okay";
bt656-supply = <&vcca_1v8>;
@@ -324,6 +347,12 @@ &tsadc {
};
&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
From 2e13dc44e6d147dad03cc7f4024ec9152f329fa9 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Wed, 15 Jul 2020 14:04:13 +0530
Subject: [PATCH] arm64: dts: rk3399pro: vmarc-som: Fix sorting nodes,
properties
Fix node, properties sorting on RockPI N10 board dts(i) files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200715083418.112003-3-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 3047b384a74090f09b994298eb5c40986275233a)
---
.../dts/rockchip/rk3399pro-rock-pi-n10.dts | 2 +-
.../dts/rockchip/rk3399pro-vmarc-som.dtsi | 35 +++++++++----------
2 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts
index a1783e7f769a..539f4005386d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts
@@ -8,8 +8,8 @@
/dts-v1/;
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
-#include "rk3399pro-vmarc-som.dtsi"
#include <arm/rockchip-radxa-dalang-carrier.dtsi>
+#include "rk3399pro-vmarc-som.dtsi"
/ {
model = "Radxa ROCK Pi N10";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index e11538171e67..121a430d6a70 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -76,8 +76,8 @@ &gmac {
&i2c0 {
clock-frequency = <400000>;
- i2c-scl-rising-time-ns = <180>;
i2c-scl-falling-time-ns = <30>;
+ i2c-scl-rising-time-ns = <180>;
status = "okay";
rk809: pmic@20 {
@@ -323,8 +323,22 @@ hym8563: hym8563@51 {
&io_domains {
status = "okay";
bt656-supply = <&vcca_1v8>;
- sdmmc-supply = <&vccio_sd>;
gpio1830-supply = <&vccio_3v0>;
+ sdmmc-supply = <&vccio_sd>;
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>;
+ };
+ };
};
&pmu_io_domains {
@@ -341,22 +355,7 @@ &sdhci {
};
&tsadc {
- status = "okay";
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
-};
-
-&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>;
- };
- };
-
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins =
- <1 RK_PC2 0 &pcfg_pull_up>;
- };
- };
+ status = "okay";
};
From 4617f4569e155d9512cdfa8defdea925cd30b9e4 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Wed, 15 Jul 2020 14:04:14 +0530
Subject: [PATCH] arm64: dts: rk3399pro: vmarc-som: Move supply regulators into
Carrier
Supply regulators are common across different variants of vmarc SOM's
since the Type C power controller IC is part of the carrier board.
So, move the supply regulators into carrier board dtsi.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200715083418.112003-4-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 4a3ca113c0f3a2ce33e51fc6a48a121b2d707d4f)
---
.../dts/rockchip-radxa-dalang-carrier.dtsi | 19 +++++++++++++++++++
.../dts/rockchip/rk3399pro-vmarc-som.dtsi | 19 -------------------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
index 176b53b8e41a..00b200a62263 100644
--- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -11,6 +11,25 @@ / {
chosen {
stdout-path = "serial2:1500000n8";
};
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
};
&gmac {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index 121a430d6a70..d8fa8127d9dc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -18,25 +18,6 @@ clkin_gmac: external-gmac-clock {
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
-
- vcc12v_dcin: vcc12v-dcin-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc12v_dcin>;
- };
};
&cpu_l0 {
From 772d02fccf2734a12aaaf22398aa70986a2868c7 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Wed, 15 Jul 2020 14:04:15 +0530
Subject: [PATCH] arm64: dts: rk3399pro: vmarc-som: Move common properties into
Carrier
Some of gmac, sdmmc node properties are common across rk3288 and
rk3399pro SOM's so move them into Carrier dtsi.
Chosen node is specific to rk3399pro configure SBC, so move it into
RockPI N10 dts.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200715083418.112003-5-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit a66bd94d0eac017e4846658750acaca2937555bb)
---
.../dts/rockchip-radxa-dalang-carrier.dtsi | 18 ++++++++++++----
.../dts/rockchip/rk3399pro-rock-pi-n10.dts | 4 ++++
.../dts/rockchip/rk3399pro-vmarc-som.dtsi | 21 +++++--------------
3 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
index 00b200a62263..450e5bb5af0b 100644
--- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -8,8 +8,11 @@
#include <dt-bindings/pwm/pwm.h>
/ {
- chosen {
- stdout-path = "serial2:1500000n8";
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
};
vcc12v_dcin: vcc12v-dcin-regulator {
@@ -33,6 +36,15 @@ vcc5v0_sys: vcc5v0-sys-regulator {
};
&gmac {
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
status = "okay";
};
@@ -48,10 +60,8 @@ &sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
vqmmc-supply = <&vccio_sd>;
- max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts
index 539f4005386d..369de5dc0ebd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts
@@ -15,4 +15,8 @@ / {
model = "Radxa ROCK Pi N10";
compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som",
"rockchip,rk3399pro";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index d8fa8127d9dc..37ed95d5f7e9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -11,13 +11,6 @@
/ {
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
-
- clkin_gmac: external-gmac-clock {
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "clkin_gmac";
- #clock-cells = <0>;
- };
};
&cpu_l0 {
@@ -42,17 +35,8 @@ &emmc_phy {
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
- assigned-clock-parents = <&clkin_gmac>;
- clock_in_out = "input";
phy-supply = <&vcc_lan>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- tx_delay = <0x28>;
- rx_delay = <0x11>;
};
&i2c0 {
@@ -335,6 +319,11 @@ &sdhci {
status = "okay";
};
+&sdmmc {
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ max-frequency = <150000000>;
+};
+
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
From 916191ead33a0ce0baec3a3cadb386c12d9a1b99 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Wed, 15 Jul 2020 14:04:16 +0530
Subject: [PATCH] dt-bindings: arm: rockchip: Add Rock Pi N8 binding
Rock Pi N8 is a Rockchip RK3288 based SBC, which has
- VMARC RK3288 SOM (as per SMARC standard) from Vamrs.
- Compatible carrier board from Radxa.
VMARC RK3288 SOM need to mount on top of dalang carrier
board for making Rock PI N8 SBC.
Add dt-bindings for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200715083418.112003-6-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 09ee4794270f0010c6397163f033f883f5bff1aa)
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index d4a4045092df..db2e35796795 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -435,6 +435,12 @@ properties:
- const: radxa,rockpi4
- const: rockchip,rk3399
+ - description: Radxa ROCK Pi N8
+ items:
+ - const: radxa,rockpi-n8
+ - const: vamrs,rk3288-vmarc-som
+ - const: rockchip,rk3288
+
- description: Radxa ROCK Pi N10
items:
- const: radxa,rockpi-n10
From 2a5e46160a746adc9a7b9b952e2000060d6da48a Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Wed, 15 Jul 2020 14:04:17 +0530
Subject: [PATCH] ARM: dts: rockchip: Add VMARC RK3288 SOM initial support
VMARC RK3288 SOM is a standard SMARC SOM design with
Rockchip RK3288 SoC, which is designed by Vamrs.
Specification:
- Rockchip RK3288
- PMIC: RK808
- eMMC: 16GB/32GB/64GB
- SD slot
- 2xUSB-2.0, 1xUSB3.0
- USB-C for power supply
- Ethernet
- HDMI, MIPI-DSI/CSI, eDP
Add initial support for VMARC RK3288 SOM, this would use
with associated carrier board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200715083418.112003-7-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit b8c564d4fa76b1314a10585eea8e97b8c621a77a)
---
arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 270 ++++++++++++++++++++++++
1 file changed, 270 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3288-vmarc-som.dtsi
diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
new file mode 100644
index 000000000000..cd61b6230f0d
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Vamrs Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+ compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288";
+
+ vccio_flash: vccio-flash-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_flash";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_io>;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vccio_flash>;
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ phy-supply = <&vcc_io>;
+ snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_io>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
+ vcc12-supply = <&vcc_io>;
+ vddio-supply = <&vcc_io>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-ramp-delay = <6000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_tp: LDO_REG1 {
+ regulator-name = "vcc_tp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_codec: LDO_REG2 {
+ regulator-name = "vcca_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_wl: LDO_REG4 {
+ regulator-name = "vcc_wl";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-name = "vdd10_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-name = "vcc_18";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_sd: SWITCH_REG1 {
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_lcd: SWITCH_REG2 {
+ regulator-name = "vcc_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ bb-supply = <&vcc_io>;
+ flash0-supply = <&vccio_flash>;
+ gpio1830-supply = <&vcc_18>;
+ gpio30-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&pinctrl {
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
+ };
+ };
+};
From 10ff584a4e12d06e7f041b37f806bd6ffac91f94 Mon Sep 17 00:00:00 2001
From: Michael Trimarchi <michael@amarulasolutions.com>
Date: Tue, 7 Jul 2020 12:12:14 +0200
Subject: [PATCH] ARM: dts: rockchip: Fix VBUS on rk3288-vyasa
Connect the voltage regulator of vbus to the otg connector.
Depending on the current mode this is enabled (in "host" mode")
or disabled (in "peripheral" mode). The regulator must be updated
if the controller is configured in "otg" mode and the status changes
between "host" and "peripheral".
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200707101214.2301768-1-michael@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 719646b76a41b8a482f8701825b635e9710ab329)
---
arch/arm/boot/dts/rk3288-vyasa.dts | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts
index 385dd59393e1..1a20854a1317 100644
--- a/arch/arm/boot/dts/rk3288-vyasa.dts
+++ b/arch/arm/boot/dts/rk3288-vyasa.dts
@@ -99,8 +99,6 @@ vusb1_5v: vusb1-5v {
pinctrl-0 = <&otg_vbus_drv>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
vin-supply = <&vsus_5v>;
};
@@ -416,6 +414,7 @@ &usb_host1 {
};
&usb_otg {
+ vbus-supply = <&vusb1_5v>;
status = "okay";
};
From 8635890fdcf41e911c4e3dd5213f3ff891513cab Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Mon, 20 Jul 2020 16:28:46 +0530
Subject: [PATCH] ARM: dts: rockchip: Add usb host0 ohci node for rk3288
rk3288 and rk3288w have a usb host0 ohci controller.
Although rk3288 ohci doesn't actually work on hardware, but
rk3288w ohci can work well.
So add usb host0 ohci node in rk3288 dtsi and boards
can then enable it if supported.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: William Wu <william.wu@rock-chips.com>
Link: https://lore.kernel.org/r/20200720105846.367776-1-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 82540defdd9cfc491f564ffb8d01911966636bc7)
---
arch/arm/boot/dts/rk3288.dtsi | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 9fa11b9f4522..68d5a58cfe88 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -616,7 +616,16 @@ usb_host0_ehci: usb@ff500000 {
status = "disabled";
};
- /* NOTE: ohci@ff520000 doesn't actually work on hardware */
+ /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
+ usb_host0_ohci: usb@ff520000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff520000 0x0 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USBHOST0>;
+ phys = <&usbphy1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
usb_host1: usb@ff540000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
From cb343a78f51f82997bce9de813c1035f15010e38 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Mon, 20 Jul 2020 16:32:28 +0530
Subject: [PATCH] ARM: dts: rockchip: Add USB for RockPI N8/N10
Radxa dalang carrier board has 2x USB 2.0 and 1x USB 3.0
ports.
This patch adds support to enable all these USB ports for
N10 and N8 combinations SBCs.
Note that the USB 3.0 port on RockPI N8 combination works
as USB 2.0 OTG since it is driven from RK3288.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200720110230.367985-1-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 417b188a985d3557b0ecb5623b27bd9843f03aec)
---
arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 42 ++++++++++
.../dts/rockchip-radxa-dalang-carrier.dtsi | 18 +++++
.../dts/rockchip/rk3399pro-vmarc-som.dtsi | 78 +++++++++++++++++++
3 files changed, 138 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
index cd61b6230f0d..78164d117248 100644
--- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
@@ -267,4 +267,46 @@ sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
};
};
+
+ vbus_host {
+ usb1_en_oc: usb1-en-oc {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ vbus_typec {
+ usb0_en_oc: usb0-en-oc {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1 {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&vbus_host {
+ enable-active-high;
+ gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */
+};
+
+&vbus_typec {
+ enable-active-high;
+ gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */
};
diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
index 450e5bb5af0b..d2b6ead148a2 100644
--- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -33,6 +33,24 @@ vcc5v0_sys: vcc5v0-sys-regulator {
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
+
+ vbus_host: vbus-host {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_en_oc>;
+ regulator-name = "vbus_host"; /* HOST-5V */
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vbus_typec: vbus-typec {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_en_oc>;
+ regulator-name = "vbus_typec";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&gmac {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index 37ed95d5f7e9..111d6cf9a4e6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -304,6 +304,18 @@ pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>;
};
};
+
+ vbus_host {
+ usb1_en_oc: usb1-en-oc {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ vbus_typec {
+ usb0_en_oc: usb0-en-oc {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
};
&pmu_io_domains {
@@ -324,8 +336,74 @@ &sdmmc {
max-frequency = <150000000>;
};
+&tcphy0 {
+ status = "okay";
+};
+
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ phy-supply = <&vbus_typec>;
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vbus_host>;
+ status = "okay";
+ };
+};
+
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_host: host-port {
+ phy-supply = <&vbus_host>;
+ status = "okay";
+ };
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+};
+
+&vbus_host {
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_en_oc>;
+};
+
+&vbus_typec {
+ enable-active-high;
+ gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_en_oc>;
+};
From 3137628a7366f1fc30748b59254d6b25c2c86efd Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Mon, 20 Jul 2020 16:32:29 +0530
Subject: [PATCH] ARM: dts: rockchip: Add HDMI out for RockPI N8/N10
This patch adds support to enable HDMI out for
N10 and N8 combinations SBCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200720110230.367985-2-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit d0cb2f30e7c033f0a8bbe98ec73dbc1db4788942)
---
arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 10 ++++++++++
.../dts/rockchip-radxa-dalang-carrier.dtsi | 20 +++++++++++++++++++
.../dts/rockchip/rk3399pro-vmarc-som.dtsi | 12 +++++++++++
3 files changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
index 78164d117248..4a373f5aa600 100644
--- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
@@ -38,6 +38,12 @@ &gmac {
snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
};
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec_c0>;
+};
+
&i2c0 {
clock-frequency = <400000>;
status = "okay";
@@ -225,6 +231,10 @@ regulator-state-mem {
};
};
+&i2c5 {
+ status = "okay";
+};
+
&io_domains {
bb-supply = <&vcc_io>;
flash0-supply = <&vccio_flash>;
diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
index d2b6ead148a2..26b53eac4706 100644
--- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -66,6 +66,10 @@ &gmac {
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
&pwm0 {
status = "okay";
};
@@ -94,3 +98,19 @@ &uart0 {
&uart2 {
status = "okay";
};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index 111d6cf9a4e6..ebccc4a153a2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -39,6 +39,12 @@ &gmac {
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+};
+
&i2c0 {
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <30>;
@@ -285,6 +291,12 @@ hym8563: hym8563@51 {
};
};
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
&io_domains {
status = "okay";
bt656-supply = <&vcca_1v8>;
From 0d5ba09fbbd6b8a5d9fc7df9d3f760842549c07f Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Mon, 20 Jul 2020 16:32:30 +0530
Subject: [PATCH] arm64: dts: rockchip: Add PCIe for RockPI N10
This patch adds support to enable PCIe for RockPI N10.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20200720110230.367985-3-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 93ca8ac2e8fcea6feb02a40edd2334144b62fc6e)
---
.../dts/rockchip/rk3399pro-vmarc-som.dtsi | 40 ++++++++++++++++++-
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
index ebccc4a153a2..5d087be04af8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
@@ -11,6 +11,18 @@
/ {
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
+
+ vcc3v3_pcie: vcc-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwr>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&cpu_l0 {
@@ -142,7 +154,8 @@ vcca_0v9: LDO_REG1 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
- regulator-off-in-suspend;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
};
};
@@ -177,7 +190,8 @@ vcca_1v8: LDO_REG4 {
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1850000>;
regulator-state-mem {
- regulator-off-in-suspend;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1850000>;
};
};
@@ -304,6 +318,22 @@ &io_domains {
sdmmc-supply = <&vccio_sd>;
};
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ max-link-speed = <2>;
+ num-lanes = <4>;
+ pinctrl-0 = <&pcie_clkreqnb_cpm>;
+ pinctrl-names = "default";
+ vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */
+ vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
@@ -311,6 +341,12 @@ hym8563_int: hym8563-int {
};
};
+ pcie {
+ pcie_pwr: pcie-pwr {
+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>;
From ec258d2b9150088af58b6935bbf3c6c3618ea8f7 Mon Sep 17 00:00:00 2001
From: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Date: Sat, 25 Jul 2020 00:59:33 +0900
Subject: [PATCH] ASoC: convert Everest ES8316 binding to yaml
This patch converts Everest Semiconductor ES8316 low power audio
CODEC binding to DT schema.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200724155933.1040501-1-katsuhiro@katsuster.net
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 92e67a9c4f206dc9c859c405e67448a8be59ac5d)
---
.../bindings/sound/everest,es8316.txt | 23 ---------
.../bindings/sound/everest,es8316.yaml | 50 +++++++++++++++++++
2 files changed, 50 insertions(+), 23 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/everest,es8316.txt
create mode 100644 Documentation/devicetree/bindings/sound/everest,es8316.yaml
diff --git a/Documentation/devicetree/bindings/sound/everest,es8316.txt b/Documentation/devicetree/bindings/sound/everest,es8316.txt
deleted file mode 100644
index 1bf03c5f2af4..000000000000
--- a/Documentation/devicetree/bindings/sound/everest,es8316.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Everest ES8316 audio CODEC
-
-This device supports both I2C and SPI.
-
-Required properties:
-
- - compatible : should be "everest,es8316"
- - reg : the I2C address of the device for I2C
-
-Optional properties:
-
- - clocks : a list of phandle, should contain entries for clock-names
- - clock-names : should include as follows:
- "mclk" : master clock (MCLK) of the device
-
-Example:
-
-es8316: codec@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- clocks = <&clks 10>;
- clock-names = "mclk";
-};
diff --git a/Documentation/devicetree/bindings/sound/everest,es8316.yaml b/Documentation/devicetree/bindings/sound/everest,es8316.yaml
new file mode 100644
index 000000000000..3b752bba748b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/everest,es8316.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/everest,es8316.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Everest ES8316 audio CODEC
+
+maintainers:
+ - Daniel Drake <drake@endlessm.com>
+ - Katsuhiro Suzuki <katsuhiro@katsuster.net>
+
+properties:
+ compatible:
+ const: everest,es8316
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: clock for master clock (MCLK)
+
+ clock-names:
+ items:
+ - const: mclk
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ es8316: codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ clocks = <&clks 10>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ };
+ };
From f5b60a176251d6e0d1716bbe62a5697a80d38089 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Tue, 21 Jul 2020 21:27:10 +0300
Subject: [PATCH] ASoC: rk3399_gru_sound: Add DAPM pins, kcontrols for jack
detection
PulseAudio (and perhaps other userspace utilities) can not detect any
jack for rk3399_gru_sound as the driver doesn't expose related Jack
kcontrols.
This patch adds two DAPM pins to the headset jack, where the
snd_soc_card_jack_new() call automatically creates "Headphones Jack" and
"Headset Mic Jack" kcontrols from them.
With an appropriate ALSA UCM config specifying JackControl fields for
the "Headphones" and "Headset" (mic) devices, PulseAudio can detect
plug/unplug events for both of them after this patch.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Link: https://lore.kernel.org/r/20200721182709.6895-1-alpernebiyasak@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit d0508b4f16049a658d68a7c276ba08296c5a76bc)
---
sound/soc/rockchip/rk3399_gru_sound.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c b/sound/soc/rockchip/rk3399_gru_sound.c
index 9539b0d024fe..3e45179638ca 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -32,6 +32,19 @@ static unsigned int dmic_wakeup_delay;
static struct snd_soc_jack rockchip_sound_jack;
+/* Headset jack detection DAPM pins */
+static struct snd_soc_jack_pin rockchip_sound_jack_pins[] = {
+ {
+ .pin = "Headphones",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ {
+ .pin = "Headset Mic",
+ .mask = SND_JACK_MICROPHONE,
+ },
+
+};
+
static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphones", NULL),
SND_SOC_DAPM_SPK("Speakers", NULL),
@@ -176,7 +189,9 @@ static int rockchip_sound_da7219_init(struct snd_soc_pcm_runtime *rtd)
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
- &rockchip_sound_jack, NULL, 0);
+ &rockchip_sound_jack,
+ rockchip_sound_jack_pins,
+ ARRAY_SIZE(rockchip_sound_jack_pins));
if (ret) {
dev_err(rtd->card->dev, "New Headset Jack failed! (%d)\n", ret);
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