36db4a668d
vopl and vopb entries were still 32 bit in the dtsi after the rest had been migrated to 64 bit.
59 lines
2.0 KiB
Diff
59 lines
2.0 KiB
Diff
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index 8f980d7..f3e0ff4 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -990,7 +990,7 @@
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vopb: vop@ff930000 {
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compatible = "rockchip,rk3288-vop";
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- reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
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+ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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@@ -1038,7 +1038,7 @@
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vopl: vop@ff940000 {
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compatible = "rockchip,rk3288-vop";
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- reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
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+ reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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@@ -1114,7 +1114,7 @@
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lvds: lvds@ff96c000 {
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compatible = "rockchip,rk3288-lvds";
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- reg = <0xff96c000 0x4000>;
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+ reg = <0x0 0xff96c000 0x0 0x4000>;
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clocks = <&cru PCLK_LVDS_PHY>;
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clock-names = "pclk_lvds";
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pinctrl-names = "lcdc";
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@@ -1224,7 +1224,7 @@
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vpu: video-codec@ff9a0000 {
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compatible = "rockchip,rk3288-vpu";
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- reg = <0xff9a0000 0x800>;
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+ reg = <0x0 0xff9a0000 0x0 0x800>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vepu", "vdpu";
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@@ -1239,7 +1239,7 @@
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vpu_service: vpu-service@ff9a0000 {
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compatible = "rockchip,vpu_service";
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- reg = <0xff9a0000 0x800>;
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+ reg = <0x0 0xff9a0000 0x0 0x800>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irq_enc", "irq_dec";
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@@ -1259,7 +1259,7 @@
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hevc_service: hevc-service@ff9c0000 {
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compatible = "rockchip,hevc_service";
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- reg = <0xff9c0000 0x400>;
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+ reg = <0x0 0xff9c0000 0x0 0x400>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irq_dec";
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clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
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