46 lines
1.6 KiB
Diff
46 lines
1.6 KiB
Diff
From 51ebc019df15b46d109bafe7068ebb6fe0b266b5 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Wed, 6 Jan 2021 19:19:01 +0100
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Subject: [PATCH 11/44] ARM: dts: sun8i: r40: Add deinterlace node
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R40 contains deinterlace core compatible to that in H3. One peculiarity
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is that RAM gate is shared with CSI1. User manual states it's separate
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but that's not true. Shared gate was verified with BSP Linux code check
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and with runtime tests (CPU crashed if CSI1 gate was not ungated).
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Link: https://lore.kernel.org/r/20210106181901.1324075-3-jernej.skrabec@siol.net
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---
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arch/arm/boot/dts/sun8i-r40.dtsi | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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--- a/arch/arm/boot/dts/sun8i-r40.dtsi
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+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
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@@ -190,6 +190,25 @@
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};
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};
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+ deinterlace: deinterlace@1400000 {
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+ compatible = "allwinner,sun8i-r40-deinterlace",
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+ "allwinner,sun8i-h3-deinterlace";
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+ reg = <0x01400000 0x20000>;
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+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
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+ <&ccu CLK_DEINTERLACE>,
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+ /*
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+ * NOTE: Contrary to what datasheet claims,
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+ * DRAM deinterlace gate doesn't exist and
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+ * it's shared with CSI1.
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+ */
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+ <&ccu CLK_DRAM_CSI1>;
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+ clock-names = "bus", "mod", "ram";
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+ resets = <&ccu RST_BUS_DEINTERLACE>;
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+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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+ interconnects = <&mbus 9>;
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+ interconnect-names = "dma-mem";
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+ };
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+
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syscon: system-control@1c00000 {
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compatible = "allwinner,sun8i-r40-system-control",
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"allwinner,sun4i-a10-system-control";
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