5b29f4dd4b
* Add MXQ target. Copy HDMI fix from odroid-c1. * meson8, MXQ: add boot from usb support, configurable dtb * MXQ: remove boot logo Built-in U-BOOT is used, so the logo will not be displayed anyway. * meson: kernel update: legacy -> 6.6, current -> 6.12 * Change Odroid C1 and Onecloud to community supported as build now passes --------- Co-authored-by: Igor Pecovnik <igor@armbian.com>
109 lines
3.7 KiB
Diff
109 lines
3.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Date: Fri, 1 Jan 2021 18:55:05 +0100
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Subject: clk: meson: meson8b: Add the mpeg_rtc_osc_sel clock
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The first input of the CLK81 clock tree uses the SoC's external
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oscillators. By default it's the 24MHz XTAL from which most frequencies
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in this SoC are derived. For power-saving purposes there's a mux to
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switch the input between the 24MHz XTAL and the 32kHz RTC oscillator.
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Add support for that mux add it to the CLK81 clock tree for a better
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representation of how the hardware is actually designed.
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Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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---
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drivers/clk/meson/meson8b.c | 26 +++++++++-
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include/dt-bindings/clock/meson8b-clkc.h | 1 +
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2 files changed, 25 insertions(+), 2 deletions(-)
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diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
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index 111111111111..222222222222 100644
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--- a/drivers/clk/meson/meson8b.c
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+++ b/drivers/clk/meson/meson8b.c
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@@ -611,7 +611,24 @@ static struct clk_regmap meson8b_mpll2 = {
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},
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};
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-static u32 mux_table_clk81[] = { 6, 5, 7 };
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+static struct clk_regmap meson8b_mpeg_rtc_osc_sel = {
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+ .data = &(struct clk_regmap_mux_data){
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+ .offset = HHI_MPEG_CLK_CNTL,
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+ .mask = 0x1,
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+ .shift = 9,
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+ },
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+ .hw.init = &(struct clk_init_data){
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+ .name = "mpeg_rtc_osc_sel",
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+ .ops = &clk_regmap_mux_ro_ops,
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+ .parent_data = (const struct clk_parent_data[]) {
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+ { .fw_name = "xtal", .index = -1, },
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+ { .fw_name = "rtc_32k", .index = -1, },
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+ },
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+ .num_parents = 2,
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+ },
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+};
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+
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+static u32 mux_table_clk81[] = { 0, 6, 5, 7 };
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static struct clk_regmap meson8b_mpeg_clk_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_MPEG_CLK_CNTL,
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@@ -628,11 +645,12 @@ static struct clk_regmap meson8b_mpeg_clk_sel = {
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* fclk_div4, fclk_div3, fclk_div5
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*/
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.parent_hws = (const struct clk_hw *[]) {
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+ &meson8b_mpeg_rtc_osc_sel.hw,
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&meson8b_fclk_div3.hw,
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&meson8b_fclk_div4.hw,
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&meson8b_fclk_div5.hw,
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},
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- .num_parents = 3,
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+ .num_parents = 4,
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},
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};
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@@ -3055,6 +3073,7 @@ static struct clk_hw *meson8_hw_clks[] = {
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[CLKID_ETH_CLK_DIV] = &meson8_eth_clk_div.hw,
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[CLKID_ETH_CLK_PHASE] = &meson8_eth_clk_phase.hw,
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[CLKID_ETH_CLK] = &meson8_eth_clk_gate.hw,
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+ [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw,
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};
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static struct clk_hw *meson8b_hw_clks[] = {
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@@ -3270,6 +3289,7 @@ static struct clk_hw *meson8b_hw_clks[] = {
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[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
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[CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
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[CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
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+ [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw,
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};
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static struct clk_hw *meson8m2_hw_clks[] = {
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@@ -3487,6 +3507,7 @@ static struct clk_hw *meson8m2_hw_clks[] = {
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[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
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[CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
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[CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
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+ [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw,
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};
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static struct clk_regmap *const meson8b_clk_regmaps[] = {
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@@ -3687,6 +3708,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
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&meson8_eth_clk_div,
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&meson8_eth_clk_phase,
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&meson8_eth_clk_gate,
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+ &meson8b_mpeg_rtc_osc_sel,
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};
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static const struct meson8b_clk_reset_line {
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diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
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index 111111111111..222222222222 100644
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--- a/include/dt-bindings/clock/meson8b-clkc.h
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+++ b/include/dt-bindings/clock/meson8b-clkc.h
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@@ -225,5 +225,6 @@
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#define CLKID_ETH_CLK_DIV 219
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#define CLKID_ETH_CLK_PHASE 220
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#define CLKID_ETH_CLK 221
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+#define CLKID_MPEG_RTC_OSC_SEL 222
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#endif /* __MESON8B_CLKC_H */
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--
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Armbian
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