167 lines
5.2 KiB
Diff
167 lines
5.2 KiB
Diff
From b0f728798d8a978d8e4f0d10d6a0aeeefdb13166 Mon Sep 17 00:00:00 2001
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Tue, 17 Oct 2017 10:29:08 +0200
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Subject: ARM64: dts: meson-gx: add VPU power domain
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This patch adds support for the VPU Power Domain nodes, and attaches the
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VPU power domain to the VPU node.
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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---
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arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 11 ++++++++
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arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 43 +++++++++++++++++++++++++++++
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arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 43 +++++++++++++++++++++++++++++
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3 files changed, 97 insertions(+)
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diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
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index ab7ce16..668d891 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
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@@ -377,6 +377,12 @@
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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reg = <0x0 0x0 0x0 0x100>;
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+ pwrc_vpu: power-controller-vpu {
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+ compatible = "amlogic,meson-gx-pwrc-vpu";
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+ #power-domain-cells = <0>;
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+ amlogic,hhi-sysctrl = <&sysctrl>;
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+ };
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+
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-gx-aoclkc";
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#clock-cells = <1>;
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@@ -454,6 +460,11 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
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+ sysctrl: system-controller@0 {
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+ compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
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+ reg = <0 0 0 0x400>;
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+ };
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+
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mailbox: mailbox@404 {
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compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
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reg = <0 0x404 0 0x4c>;
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diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
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index ead895a..6904872 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
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@@ -694,6 +694,48 @@
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};
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};
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+&pwrc_vpu {
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+ resets = <&reset RESET_VIU>,
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+ <&reset RESET_VENC>,
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+ <&reset RESET_VCBUS>,
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+ <&reset RESET_BT656>,
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+ <&reset RESET_DVIN_RESET>,
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+ <&reset RESET_RDMA>,
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+ <&reset RESET_VENCI>,
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+ <&reset RESET_VENCP>,
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+ <&reset RESET_VDAC>,
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+ <&reset RESET_VDI6>,
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+ <&reset RESET_VENCL>,
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+ <&reset RESET_VID_LOCK>;
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+ clocks = <&clkc CLKID_VPU>,
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+ <&clkc CLKID_VAPB>;
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+ clock-names = "vpu", "vapb";
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+ /*
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+ * VPU clocking is provided by two identical clock paths
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+ * VPU_0 and VPU_1 muxed to a single clock by a glitch
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+ * free mux to safely change frequency while running.
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+ * Same for VAPB but with a final gate after the glitch free mux.
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+ */
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+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
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+ <&clkc CLKID_VPU_0>,
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+ <&clkc CLKID_VPU>, /* Glitch free mux */
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+ <&clkc CLKID_VAPB_0_SEL>,
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+ <&clkc CLKID_VAPB_0>,
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+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
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+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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+ <0>, /* Do Nothing */
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+ <&clkc CLKID_VPU_0>,
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+ <&clkc CLKID_FCLK_DIV4>,
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+ <0>, /* Do Nothing */
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+ <&clkc CLKID_VAPB_0>;
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+ assigned-clock-rates = <0>, /* Do Nothing */
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+ <666666666>,
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+ <0>, /* Do Nothing */
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+ <0>, /* Do Nothing */
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+ <250000000>,
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+ <0>; /* Do Nothing */
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+};
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+
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&saradc {
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compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
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clocks = <&xtal>,
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@@ -763,4 +805,5 @@
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&vpu {
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compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
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+ power-domains = <&pwrc_vpu>;
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};
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diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
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index 8ed981f..49b8ec1 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
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@@ -644,6 +644,48 @@
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};
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};
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+&pwrc_vpu {
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+ resets = <&reset RESET_VIU>,
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+ <&reset RESET_VENC>,
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+ <&reset RESET_VCBUS>,
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+ <&reset RESET_BT656>,
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+ <&reset RESET_DVIN_RESET>,
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+ <&reset RESET_RDMA>,
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+ <&reset RESET_VENCI>,
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+ <&reset RESET_VENCP>,
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+ <&reset RESET_VDAC>,
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+ <&reset RESET_VDI6>,
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+ <&reset RESET_VENCL>,
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+ <&reset RESET_VID_LOCK>;
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+ clocks = <&clkc CLKID_VPU>,
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+ <&clkc CLKID_VAPB>;
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+ clock-names = "vpu", "vapb";
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+ /*
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+ * VPU clocking is provided by two identical clock paths
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+ * VPU_0 and VPU_1 muxed to a single clock by a glitch
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+ * free mux to safely change frequency while running.
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+ * Same for VAPB but with a final gate after the glitch free mux.
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+ */
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+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
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+ <&clkc CLKID_VPU_0>,
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+ <&clkc CLKID_VPU>, /* Glitch free mux */
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+ <&clkc CLKID_VAPB_0_SEL>,
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+ <&clkc CLKID_VAPB_0>,
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+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
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+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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+ <0>, /* Do Nothing */
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+ <&clkc CLKID_VPU_0>,
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+ <&clkc CLKID_FCLK_DIV4>,
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+ <0>, /* Do Nothing */
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+ <&clkc CLKID_VAPB_0>;
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+ assigned-clock-rates = <0>, /* Do Nothing */
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+ <666666666>,
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+ <0>, /* Do Nothing */
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+ <0>, /* Do Nothing */
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+ <250000000>,
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+ <0>; /* Do Nothing */
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+};
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+
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&saradc {
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compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
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clocks = <&xtal>,
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@@ -713,4 +755,5 @@
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&vpu {
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compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
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+ power-domains = <&pwrc_vpu>;
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};
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--
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cgit v1.1
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