23604e8a0d
* Introducing Rockchip rk322x SoC support Main features: - Legacy kernel flavour based upon stable v2.x rk3288 Rockchip branch (https://github.com/rockchip-linux/kernel/tree/stable-4.4-rk3288-linux-v2.x) - Current kernel flavour based on mainline 5.6.y kernel - Mainline u-boot (v2020.04) - Single generic tv box target (rk322x-box) which boots on all the known tv boxes - Hardware devices (eMMC/NAND, led wiring configuration, SoC variant selection) modulation done by user at runtime via device tree overlays - a script (rk322x-config) is provided for autodetection and simple configuration by inexperienced users; - Bits added to armbian-hardware-optimization to set affinity for irq handlers - rk322x-box targets already added to targets.conf for automatic image creation * Removed disabled patches * Restored mysteriously removed comment character
43 lines
1.7 KiB
Diff
43 lines
1.7 KiB
Diff
From a05e0306d9793da2bb76a6c712ae20ecc3af6d98 Mon Sep 17 00:00:00 2001
|
|
From: Alex Bee <knaerzche@gmail.com>
|
|
Date: Thu, 27 Feb 2020 13:50:52 +0100
|
|
Subject: [PATCH] rockchip: sdram: fix dram_init_banksize with CONFIG_SPL_OPTEE
|
|
|
|
Currently 2.5 GB is calculated as DRAM size for a 1 GB RK322x board when CONFIG_SPL_OPTEE is set.
|
|
|
|
gd->bd->bi_dram[0].start (which is basically CONFIG_SYS_SDRAM_BASE) must not be taken into consideration
|
|
for calculation of second bank size, since this offset is already included in calculation of "top".
|
|
After applying this patch 992 MB (1024 MB -32 MB reserved for trustos) is calculated.
|
|
|
|
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
|
---
|
|
arch/arm/mach-rockchip/sdram.c | 6 ++----
|
|
1 file changed, 2 insertions(+), 4 deletions(-)
|
|
|
|
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
|
|
index 530644c043..05bc0c14e5 100644
|
|
--- a/arch/arm/mach-rockchip/sdram.c
|
|
+++ b/arch/arm/mach-rockchip/sdram.c
|
|
@@ -55,16 +55,14 @@ int dram_init_banksize(void)
|
|
- CONFIG_SYS_SDRAM_BASE;
|
|
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
|
|
tos_parameter->tee_mem.size;
|
|
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
|
|
- + top - gd->bd->bi_dram[1].start;
|
|
+ gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
|
|
} else {
|
|
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
|
gd->bd->bi_dram[0].size = 0x8400000;
|
|
/* Reserve 32M for OPTEE with TA */
|
|
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
|
|
+ gd->bd->bi_dram[0].size + 0x2000000;
|
|
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
|
|
- + top - gd->bd->bi_dram[1].start;
|
|
+ gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
|
|
}
|
|
#else
|
|
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
|
--
|
|
2.17.1
|
|
|