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armbian-build/patch/kernel/sun8i-default/0004-HACK-Make-Mali400-driver-work-on-H3.patch
Igor Pecovnik 73425568ad New / updated sun8i (updated) kernel patches
2016-04-13 09:25:21 +02:00

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From 2586c38ac17a918a71002bbd74357ca3f01cacb6 Mon Sep 17 00:00:00 2001
From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Date: Mon, 7 Dec 2015 09:05:52 +0200
Subject: [PATCH 04/27] HACK: Make Mali400 driver work on H3
It is not a very clean patch, but it works. There is no power
management and Mali is clocked at a relatively low speed (252 MHz)
in order to avoid excessive overheating. This is fast enough for
lima-memtester anyway.
The clock setup code is partially based on the Mali r4p0 driver
sources from "modules/mali/DX910-SW-99002-r4p0-00rel0"
---
drivers/gpu/mali/Makefile | 2 +-
.../mali/mali/arch-ca7-virtex820-m400-2/config.h | 14 +--
drivers/gpu/mali/mali/common/mali_mem_validation.c | 17 +--
drivers/gpu/mali/mali/linux/mali_ukk_mem.c | 1 -
.../mali/mali/platform/mali400-pmu/mali_platform.c | 114 +++++++--------------
5 files changed, 49 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/mali/Makefile b/drivers/gpu/mali/Makefile
index 9549390..496f3aa 100644
--- a/drivers/gpu/mali/Makefile
+++ b/drivers/gpu/mali/Makefile
@@ -1,6 +1,6 @@
# Configuration for A10
-ifdef CONFIG_ARCH_SUN7I
+ifdef CONFIG_ARCH_SUN8IW7P1
CONFIG:=ca7-virtex820-m400-2
MALI_PLATFORM_FILE:=platform/${CONFIG}/mali_platform.c
export MALI_PLATFORM_FILE
diff --git a/drivers/gpu/mali/mali/arch-ca7-virtex820-m400-2/config.h b/drivers/gpu/mali/mali/arch-ca7-virtex820-m400-2/config.h
index 08dfbfb..cf2158d 100644
--- a/drivers/gpu/mali/mali/arch-ca7-virtex820-m400-2/config.h
+++ b/drivers/gpu/mali/mali/arch-ca7-virtex820-m400-2/config.h
@@ -17,13 +17,13 @@
hardcode the irq to make it work on allwinner a20 platform
*/
#define SW_INT_START 32
-#define SW_INT_IRQNO_GPU_GP (69 + SW_INT_START)
-#define SW_INT_IRQNO_GPU_GPMMU (70 + SW_INT_START)
-#define SW_INT_IRQNO_GPU_PP0 (71 + SW_INT_START)
-#define SW_INT_IRQNO_GPU_PPMMU0 (72 + SW_INT_START)
-#define SW_INT_IRQNO_GPU_PMU (73 + SW_INT_START)
-#define SW_INT_IRQNO_GPU_PP1 (74 + SW_INT_START)
-#define SW_INT_IRQNO_GPU_PPMMU1 (75 + SW_INT_START)
+#define SW_INT_IRQNO_GPU_GP (97 + SW_INT_START)
+#define SW_INT_IRQNO_GPU_GPMMU (98 + SW_INT_START)
+#define SW_INT_IRQNO_GPU_PP0 (99 + SW_INT_START)
+#define SW_INT_IRQNO_GPU_PPMMU0 (100 + SW_INT_START)
+#define SW_INT_IRQNO_GPU_PMU (101 + SW_INT_START)
+#define SW_INT_IRQNO_GPU_PP1 (102 + SW_INT_START)
+#define SW_INT_IRQNO_GPU_PPMMU1 (103 + SW_INT_START)
static _mali_osk_resource_t arch_configuration [] =
{
diff --git a/drivers/gpu/mali/mali/common/mali_mem_validation.c b/drivers/gpu/mali/mali/common/mali_mem_validation.c
index 4a5b88c..8ba57a8 100644
--- a/drivers/gpu/mali/mali/common/mali_mem_validation.c
+++ b/drivers/gpu/mali/mali/common/mali_mem_validation.c
@@ -14,11 +14,6 @@
#define MALI_INVALID_MEM_ADDR 0xFFFFFFFF
-extern unsigned long fb0_start;
-extern unsigned long fb0_size;
-extern unsigned long fb1_start;
-extern unsigned long fb1_size;
-
typedef struct
{
u32 phys_base; /**< Mali physical base of the memory, page aligned */
@@ -76,14 +71,6 @@ static _mali_osk_errcode_t validation_check_helper(u32 phys_addr, u32 size,
_mali_osk_errcode_t mali_mem_validation_check(u32 phys_addr, u32 size)
{
- _mali_mem_validation_t fb0 = { fb0_start, fb0_size };
- _mali_mem_validation_t fb1 = { fb1_start, fb1_size };
-
- if (validation_check_helper(phys_addr, size, fb0) == _MALI_OSK_ERR_OK ||
- validation_check_helper(phys_addr, size, fb1) == _MALI_OSK_ERR_OK ||
- validation_check_helper(phys_addr, size, mali_mem_validator) == _MALI_OSK_ERR_OK)
- return _MALI_OSK_ERR_OK;
-
- MALI_PRINT_ERROR(("MALI PHYSICAL RANGE VALIDATION ERROR: The range supplied was: phys_base=0x%08X, size=0x%08X\n", phys_addr, size));
- return _MALI_OSK_ERR_FAULT;
+ /* Accept any memory region without validation */
+ return _MALI_OSK_ERR_OK;
}
diff --git a/drivers/gpu/mali/mali/linux/mali_ukk_mem.c b/drivers/gpu/mali/mali/linux/mali_ukk_mem.c
index 3951831..b679108 100644
--- a/drivers/gpu/mali/mali/linux/mali_ukk_mem.c
+++ b/drivers/gpu/mali/mali/linux/mali_ukk_mem.c
@@ -9,7 +9,6 @@
*/
#include <linux/fs.h> /* file system operations */
#include <asm/uaccess.h> /* user space access */
-#include <plat/memory.h>
#include "mali_ukk.h"
#include "mali_osk.h"
diff --git a/drivers/gpu/mali/mali/platform/mali400-pmu/mali_platform.c b/drivers/gpu/mali/mali/platform/mali400-pmu/mali_platform.c
index d43bde0..54e50d5 100644
--- a/drivers/gpu/mali/mali/platform/mali400-pmu/mali_platform.c
+++ b/drivers/gpu/mali/mali/platform/mali400-pmu/mali_platform.c
@@ -17,105 +17,69 @@
#include "mali_platform.h"
#include "mali_mem_validation.h"
-#include <linux/module.h>
+#include <linux/mali/mali_utgard.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <linux/regulator/consumer.h>
#include <linux/clk.h>
+#include <linux/clk/sunxi_name.h>
+#include <linux/clk-private.h>
+#include <linux/pm_runtime.h>
+#include <linux/dma-mapping.h>
+#include <linux/stat.h>
+#include <linux/delay.h>
#include <mach/irqs.h>
-#include <mach/clock.h>
-#include <plat/sys_config.h>
-#include <plat/memory.h>
-
-int mali_clk_div = 3;
-module_param(mali_clk_div, int, S_IRUSR | S_IWUSR | S_IWGRP | S_IRGRP | S_IROTH);
-MODULE_PARM_DESC(mali_clk_div, "Clock divisor for mali");
-
-struct clk *h_ahb_mali, *h_mali_clk, *h_ve_pll;
-int mali_clk_flag=0;
+#include <mach/sys_config.h>
+#include <mach/platform.h>
+static struct clk *mali_clk = NULL;
+static struct clk *gpu_pll = NULL;
_mali_osk_errcode_t mali_platform_init(void)
{
- unsigned long rate;
- int clk_div;
- int mali_used = 0;
-
- //get mali ahb clock
- h_ahb_mali = clk_get(NULL, "ahb_mali");
- if(!h_ahb_mali){
- MALI_PRINT(("try to get ahb mali clock failed!\n"));
- }
- //get mali clk
- h_mali_clk = clk_get(NULL, "mali");
- if(!h_mali_clk){
- MALI_PRINT(("try to get mali clock failed!\n"));
- }
+ int freq = 252; /* 252 MHz */
- h_ve_pll = clk_get(NULL, "ve_pll");
- if(!h_ve_pll){
- MALI_PRINT(("try to get ve pll clock failed!\n"));
- }
+ gpu_pll = clk_get(NULL, PLL_GPU_CLK);
- //set mali parent clock
- if(clk_set_parent(h_mali_clk, h_ve_pll)){
- MALI_PRINT(("try to set mali clock source failed!\n"));
+ if (!gpu_pll || IS_ERR(gpu_pll)) {
+ printk(KERN_ERR "Failed to get gpu pll clock!\n");
+ return -1;
}
- //set mali clock
- rate = clk_get_rate(h_ve_pll);
-
- if(!script_parser_fetch("mali_para", "mali_used", &mali_used, 1)) {
- if (mali_used == 1) {
- if (!script_parser_fetch("mali_para", "mali_clkdiv", &clk_div, 1)) {
- if (clk_div > 0) {
- pr_info("mali: use config clk_div %d\n", clk_div);
- mali_clk_div = clk_div;
- }
- }
- }
+ mali_clk = clk_get(NULL, GPU_CLK);
+ if (!mali_clk || IS_ERR(mali_clk)) {
+ printk(KERN_ERR "Failed to get mali clock!\n");
+ return -1;
}
- pr_info("mali: clk_div %d\n", mali_clk_div);
- rate /= mali_clk_div;
-
- if(clk_set_rate(h_mali_clk, rate)){
- MALI_PRINT(("try to set mali clock failed!\n"));
+ if (clk_set_rate(gpu_pll, freq * 1000 * 1000)) {
+ printk(KERN_ERR "Failed to set gpu pll clock!\n");
+ return -1;
}
- if(clk_reset(h_mali_clk,0)){
- MALI_PRINT(("try to reset release failed!\n"));
+ if (clk_set_rate(mali_clk, freq * 1000 * 1000)) {
+ printk(KERN_ERR "Failed to set mali clock!\n");
+ return -1;
}
+
+ if (mali_clk->enable_count == 0) {
+ if (clk_prepare_enable(gpu_pll))
+ printk(KERN_ERR "Failed to enable gpu pll!\n");
- MALI_PRINT(("mali clock set completed, clock is %d Hz\n", rate));
-
-
- /*enable mali axi/apb clock*/
- if(mali_clk_flag == 0)
- {
- //printk(KERN_WARNING "enable mali clock\n");
- //MALI_PRINT(("enable mali clock\n"));
- mali_clk_flag = 1;
- if(clk_enable(h_ahb_mali))
- {
- MALI_PRINT(("try to enable mali ahb failed!\n"));
- }
- if(clk_enable(h_mali_clk))
- {
- MALI_PRINT(("try to enable mali clock failed!\n"));
- }
+ if (clk_prepare_enable(mali_clk))
+ printk(KERN_ERR "Failed to enable mali clock!\n");
}
+ pr_info("mali clk: %d MHz\n", freq);
MALI_SUCCESS;
}
_mali_osk_errcode_t mali_platform_deinit(void)
{
- /*close mali axi/apb clock*/
- if(mali_clk_flag == 1)
- {
- //MALI_PRINT(("disable mali clock\n"));
- mali_clk_flag = 0;
- clk_disable(h_mali_clk);
- clk_disable(h_ahb_mali);
+ if (mali_clk->enable_count == 1) {
+ clk_disable_unprepare(mali_clk);
+ clk_disable_unprepare(gpu_pll);
}
MALI_SUCCESS;
--
1.9.1
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