45 lines
1.5 KiB
Diff
45 lines
1.5 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Guillaume La Roque <glaroque@baylibre.com>
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Date: Sun, 23 Nov 2025 18:14:10 +0100
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Subject: [PATCH] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference
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for S922X CPUs
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The original addition of cache information for the Amlogic S922X SoC
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used the wrong next-level cache node for CPU cores 100 and 101,
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incorrectly referencing `l2_cache_l`. These cores actually belong to
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the big cluster and should reference `l2_cache_b`. Update the device
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tree accordingly.
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Fixes: e7f85e6c155a ("arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC")
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Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
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---
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arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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index f04efa828256..23358d94844c 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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@@ -87,7 +87,7 @@ cpu100: cpu@100 {
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i-cache-line-size = <32>;
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i-cache-size = <0x8000>;
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i-cache-sets = <32>;
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- next-level-cache = <&l2_cache_l>;
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+ next-level-cache = <&l2_cache_b>;
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#cooling-cells = <2>;
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};
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@@ -103,7 +103,7 @@ cpu101: cpu@101 {
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i-cache-line-size = <32>;
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i-cache-size = <0x8000>;
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i-cache-sets = <32>;
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- next-level-cache = <&l2_cache_l>;
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+ next-level-cache = <&l2_cache_b>;
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#cooling-cells = <2>;
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};
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--
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2.34.1
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