148 lines
5.8 KiB
Diff
148 lines
5.8 KiB
Diff
From 2ffa6ba6e67706f195b1938c5f7e8a385252bd8e Mon Sep 17 00:00:00 2001
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Wed, 14 Nov 2018 16:48:50 +0100
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Subject: [PATCH] drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support
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Add support for SCDC Setup for TMDS Clock > 3.4GHz and enable TMDS
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Scrambling when supported or mandatory.
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This patch also adds an helper to setup the control bit to support
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the hight TMDS Bit Period/TMDS Clock-Period Ratio as required with
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TMDS Clock > 3.4GHz for HDMI2.0 3840x2160@60/50 modes.
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These changes were based on work done by Huicong Xu <xhc@rock-chips.com>
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and Nickey Yang <nickey.yang@rock-chips.com> to support HDMI2.0 modes
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on the Rockchip 4.4 BSP kernel at [1]
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[1] https://github.com/rockchip-linux/kernel/tree/release-4.4
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Cc: Nickey Yang <nickey.yang@rock-chips.com>
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Cc: Huicong Xu <xhc@rock-chips.com>
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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---
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drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 45 ++++++++++++++++++++++++++++---
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drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 +
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include/drm/bridge/dw_hdmi.h | 1 +
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3 files changed, 44 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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index 1fc1270..2a30d83 100644
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--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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@@ -28,6 +28,7 @@
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_encoder_slave.h>
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+#include <drm/drm_scdc_helper.h>
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#include <drm/bridge/dw_hdmi.h>
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#include <uapi/linux/media-bus-format.h>
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@@ -1026,6 +1027,20 @@ void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
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}
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EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
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+void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
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+{
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+ unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mpixelclock;
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+
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+ /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
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+ if (hdmi->connector.display_info.hdmi.scdc.supported) {
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+ if (mtmdsclock > 340000000)
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+ drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
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+ else
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+ drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
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+ }
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+}
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+EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
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+
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static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
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{
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hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
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@@ -1351,11 +1366,12 @@ static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
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static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
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{
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+ bool is_hdmi2_sink = hdmi->connector.display_info.hdmi.scdc.supported;
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struct hdmi_avi_infoframe frame;
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u8 val;
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/* Initialise info frame from DRM mode */
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- drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
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+ drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2_sink);
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if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
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frame.colorspace = HDMI_COLORSPACE_YUV444;
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@@ -1514,7 +1530,8 @@ static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
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static void hdmi_av_composer(struct dw_hdmi *hdmi,
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const struct drm_display_mode *mode)
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{
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- u8 inv_val;
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+ u8 inv_val, bytes;
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+ struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
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struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
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int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
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unsigned int vdisplay;
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@@ -1524,7 +1541,9 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
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dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
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/* Set up HDMI_FC_INVIDCONF */
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- inv_val = (hdmi->hdmi_data.hdcp_enable ?
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+ inv_val = (hdmi->hdmi_data.hdcp_enable ||
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+ vmode->mpixelclock > 340000000 ||
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+ hdmi_info->scdc.scrambling.low_rates ?
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HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
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HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
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@@ -1573,6 +1592,26 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
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vsync_len /= 2;
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}
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+ /* Scrambling Control */
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+ if (hdmi_info->scdc.supported) {
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+ if (vmode->mpixelclock > 340000000 ||
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+ hdmi_info->scdc.scrambling.low_rates) {
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+ drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
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+ &bytes);
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+ drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
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+ bytes);
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+ drm_scdc_set_scrambling(&hdmi->i2c->adap, 1);
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+ hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
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+ HDMI_MC_SWRSTZ);
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+ hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
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+ } else {
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+ hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
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+ hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
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+ HDMI_MC_SWRSTZ);
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+ drm_scdc_set_scrambling(&hdmi->i2c->adap, 0);
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+ }
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+ }
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+
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/* Set up horizontal active pixel width */
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hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
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hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
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diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
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index 9d90eb9..3f3c616 100644
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--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
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+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
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@@ -255,6 +255,7 @@
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#define HDMI_FC_MASK2 0x10DA
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#define HDMI_FC_POL2 0x10DB
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#define HDMI_FC_PRCONF 0x10E0
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+#define HDMI_FC_SCRAMBLER_CTRL 0x10E1
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#define HDMI_FC_GMD_STAT 0x1100
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#define HDMI_FC_GMD_EN 0x1101
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diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
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index ccb5aa8..d7cc5d0 100644
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--- a/include/drm/bridge/dw_hdmi.h
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+++ b/include/drm/bridge/dw_hdmi.h
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@@ -156,6 +156,7 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
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void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
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void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
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void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
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+void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi);
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/* PHY configuration */
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void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
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