1a12994e79
* [Early WIP] Update sunxi-next to kernel 4.17 * Switch Allwinner 32 and 64bit to U-boot 2018.05 * Adjust patched for 4.17.y / sunxi-next - adjust both configurations - removing FAT support from u-boot (breaks if you try to save) Tested those boards: Cubietruck: wlan fails http://ix.io/1fYS USB OK, HDMI yes Bananapi R40: http://ix.io/1fZm USB OK, HDMI yes Lime A64: USB no, HDMI no, wireless buggy, eMMC yes Orangepi prime H5: OK http://ix.io/1fZJ DVFS no Orangepi2e: DVFS OK, HDMI OK, net OK, wifi OK, eMMC ok, http://ix.io/1fZT * Kernel config update, enabling HDMI on CT+ * Trying to fix A64 HDMI but failed. Fixed M64 ethernet instead * Update orangepioneplus.wip * Update orangepioneplus.wip * Fix H6 build process * Add regulator bits for Orangepizero+, thanks to @5kft * add H5 support for optional 1.3v regulator and 1.3GHz operation This patch adds two optional overlays that can be used to: 1) enable the 1.1v/1.3v regulator on boards that provide the necessary compatible H/W support 2) modify the default CPU clock operating table to add new 1.2GHz and 1.3GHz clocks Note that the generated regulator overlay will only support boards whose 1.1v/1.3v regulator is controlled by GPIO PL6. * updates for the NanoPi NEO Plus2 This change introduces a patch that provides two changes for the NanoPi NEO Plus2: * Configure the "cpu0" to use the "vdd_cpux" regulator; this enables the ability to use higher CPU clocks * Correct the configurations of the on-board power and status LEDs * Adjust nightly building and few boards config cleanup
71 lines
2.0 KiB
Diff
71 lines
2.0 KiB
Diff
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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index 4fc5c3c..ea9ed0f 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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@@ -44,6 +44,65 @@
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#include <dt-bindings/thermal/thermal.h>
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/ {
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+ cpu_opp_table: opp_table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp@408000000 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <1000000 1000000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@648000000 {
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+ opp-hz = /bits/ 64 <648000000>;
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+ opp-microvolt = <1040000 1040000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@816000000 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <1080000 1080000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@912000000 {
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+ opp-hz = /bits/ 64 <912000000>;
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+ opp-microvolt = <1120000 1120000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@960000000 {
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+ opp-hz = /bits/ 64 <960000000>;
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+ opp-microvolt = <1160000 1160000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <1200000 1200000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1240000 1240000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1260000 1260000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1152000000 {
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+ opp-hz = /bits/ 64 <1152000000>;
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+ opp-microvolt = <1300000 1300000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+ };
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+
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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