armbian-build/patch/kernel/rockchip-dev/4005-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch
Miouyouyou 5ffefd40ab
[RFC] RK3288 : Add HDMI resolutions (#1887)
* patch: kernel: rockchip-dev: Handle more resolutions with HDMI (β)

The added patch add more PLL configurations, in order to satisfy
more HDMI frequencies requirements.
This should allow users to benefit from more resolutions.

However, this is fairly untested. I only tested it on my 1080p
screen and, yeah, it works but so does the kernel without this
patch.

Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>

* patch: kernel: rockchip-dev: Handle more resolutions with HDMI (β)

Now with proper patches names.

Anyway :

The added patch add more PLL configurations, in order to satisfy
more HDMI frequencies requirements.
This should allow users to benefit from more resolutions.

However, this is fairly untested. I only tested it on my 1080p
screen and, yeah, it works but it also does without this
patch.

So could anyone test this with the following configurations ?

* [ ] A HDMI 4K screen
* [ ] A HDMI 1366x768 screen resolution
* [ ] A VGA screen with a VGA to HDMI adapter
* [ ] A DVI screen with a DVI to HDMI adapter

Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>

* Using the patches provided by @Kwiboo for HDMI

This provides me way more resolutions, including interlaced modes.

I don't see 4K modes, though the screen attached can't do it,
so I still don't know if that can help provided 4K modes on mainline
kernels.

Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>

* Support for 4K screens

Using fixes provided by @czak

Tested and approved by @czak too !

Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
2020-05-24 23:08:01 +02:00

47 lines
1.6 KiB
Diff

From 435bdc2bdfd2bd37e96b42c7c972ce271e06d90c Mon Sep 17 00:00:00 2001
From: Douglas Anderson <dianders@chromium.org>
Date: Mon, 11 Jul 2016 19:05:36 +0800
Subject: [PATCH 06/14] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always
Jitter was improved by lowering the MPLL bandwidth to account for high
frequency noise in the rk3288 PLL. In each case MPLL bandwidth was
lowered only enough to get us a comfortable margin. We believe that
lowering the bandwidth like this is safe given sufficient testing.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 7f56d8c34..7d7ee5b26 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -159,20 +159,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
/* pixelclk bpp8 bpp10 bpp12 */
{
- 40000000, { 0x0018, 0x0018, 0x0018 },
- }, {
- 65000000, { 0x0028, 0x0028, 0x0028 },
- }, {
- 66000000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 74250000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 83500000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 146250000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 148500000, { 0x0000, 0x0038, 0x0038 },
- }, {
+ 600000000, { 0x0000, 0x0000, 0x0000 },
+ }, {
~0UL, { 0x0000, 0x0000, 0x0000},
}
};
--
2.26.2