53 lines
1.8 KiB
Diff
53 lines
1.8 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Vyacheslav Bocharov <adeep@lexina.in>
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Date: Mon, 7 Nov 2022 16:19:08 +0300
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Subject: arm64: amlogic: dts: meson: update meson-axg device-tree for new
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core, tx, rx phase clock settings.
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Use phase 270 for core MMC clock on axg meson boards.
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Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
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---
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arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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index 111111111111..222222222222 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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@@ -13,6 +13,7 @@
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#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
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#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
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#include <dt-bindings/power/meson-axg-power.h>
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+#include <dt-bindings/mmc/meson-gx-mmc.h>
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/ {
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compatible = "amlogic,meson-axg";
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@@ -1958,10 +1958,11 @@ sd_emmc_b: mmc@5000 {
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status = "disabled";
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clocks = <&clkc CLKID_SD_EMMC_B>,
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<&clkc CLKID_SD_EMMC_B_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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+ amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
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resets = <&reset RESET_SD_EMMC_B>;
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assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
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assigned-clock-rates = <24000000>;
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};
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@@ -1973,10 +1974,11 @@ sd_emmc_c: mmc@7000 {
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status = "disabled";
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clocks = <&clkc CLKID_SD_EMMC_C>,
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<&clkc CLKID_SD_EMMC_C_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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+ amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
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resets = <&reset RESET_SD_EMMC_C>;
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assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
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assigned-clock-rates = <24000000>;
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};
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--
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Armbian
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