a73e79a73f
- Fix dram, mmc for h616. - The prefix is missing if we use OF_UPSTREAM - upstream: arm64: sun50i-h616: sync with sunxi-6.12 kernel - upstream: arm64: Add sun50i-h618-bananapi-m4-berry.dts
77 lines
2.8 KiB
Diff
77 lines
2.8 KiB
Diff
From 3e51ab767091957ccfeb4ba778dd546234044a4b Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Sun, 9 Mar 2025 07:31:42 +0100
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Subject: sunxi: h616: dram: Rework size detection
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Since there is quite a few possible DRAM configurations in terms of bus
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width, rank and rows and columns count, size detection algorithm must be
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very careful not to test combination which would be bigger than H616 is
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actually capable of handling.
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Ideally, we should always detect memory aliasing, even for 4 GB memory
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size, which is the maximum amount of memory that H616 is capable of
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handling. For this reason, we have to configure minimum amount of
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supported rows when testing for columns and vice versa. This way test
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code will never step out of 4 GB boundary.
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While at it, check for 17 rows maximum. This aligns code with BSP DRAM
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driver. There is probably no such configuration which would make sense
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with 4 GB memory.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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arch/arm/mach-sunxi/dram_sun50i_h616.c | 20 ++++++++++++--------
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1 file changed, 12 insertions(+), 8 deletions(-)
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diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
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index b3554cc64bf5..6f84e59e39cd 100644
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--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
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+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
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@@ -1363,7 +1363,7 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para,
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static void mctl_auto_detect_dram_size(const struct dram_para *para,
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struct dram_config *config)
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{
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- unsigned int shift;
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+ unsigned int shift, cols, rows;
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/* max. config for columns, but not rows */
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config->cols = 11;
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@@ -1373,23 +1373,27 @@ static void mctl_auto_detect_dram_size(const struct dram_para *para,
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shift = config->bus_full_width + 1;
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/* detect column address bits */
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- for (config->cols = 8; config->cols < 11; config->cols++) {
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- if (mctl_mem_matches(1ULL << (config->cols + shift)))
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+ for (cols = 8; cols < 11; cols++) {
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+ if (mctl_mem_matches(1ULL << (cols + shift)))
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break;
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}
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- debug("detected %u columns\n", config->cols);
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+ debug("detected %u columns\n", cols);
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/* reconfigure to make sure that all active rows are accessible */
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- config->rows = 18;
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+ config->cols = 8;
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+ config->rows = 17;
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mctl_core_init(para, config);
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/* detect row address bits */
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shift = config->bus_full_width + 4 + config->cols;
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- for (config->rows = 13; config->rows < 18; config->rows++) {
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- if (mctl_mem_matches(1ULL << (config->rows + shift)))
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+ for (rows = 13; rows < 17; rows++) {
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+ if (mctl_mem_matches(1ULL << (rows + shift)))
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break;
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}
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- debug("detected %u rows\n", config->rows);
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+ debug("detected %u rows\n", rows);
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+
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+ config->cols = cols;
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+ config->rows = rows;
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}
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static unsigned long mctl_calc_size(const struct dram_config *config)
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--
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2.35.3
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