[ rockchip ] re-enable patch for general video parameters
This commit is contained in:
Thomas McKahan
parent
a304fab39d
commit
ff9a0a3bbe
@ -322,39 +322,6 @@ index 0161f80ab964..6cf391405ad6 100644
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{ ~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
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};
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From 0377b8c27f4b56b0b6f1fc8af11cde6ab8517c3b Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Tue, 12 Dec 2017 00:37:27 +0100
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Subject: [PATCH] clk: rockchip: fix round rate
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---
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drivers/clk/rockchip/clk-pll.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
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index addcdb07553a..e3d7a9ee1078 100644
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--- a/drivers/clk/rockchip/clk-pll.c
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+++ b/drivers/clk/rockchip/clk-pll.c
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@@ -356,6 +356,17 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
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static long rockchip_pll_round_rate(struct clk_hw *hw,
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unsigned long drate, unsigned long *prate)
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{
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+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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+ const struct rockchip_pll_rate_table *rate;
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+
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+ /* Get required rate settings from table */
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+ rate = rockchip_get_pll_settings(pll, drate);
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+ if (!rate) {
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+ pr_debug("%s: Invalid rate : %lu for pll clk %s\n", __func__,
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+ drate, __clk_get_name(hw->clk));
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+ return -EINVAL;
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+ }
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+
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return drate;
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}
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From c4bc7e7f44f76a7f6f2374956fd68cab657f1eb3 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 21 Jan 2018 17:20:00 +0100
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@ -981,112 +948,3 @@ index a0e25278232b..f56f3224a1c9 100644
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hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
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hdmi_writeb(hdmi, frame.eotf, HDMI_FC_DRM_PB0);
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From 13040ab461d79e1dc720677eb462ace745b33b84 Mon Sep 17 00:00:00 2001
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From: Nickey Yang <nickey.yang@rock-chips.com>
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Date: Mon, 17 Jul 2017 16:35:34 +0800
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Subject: [PATCH] MINIARM: set npll be used for hdmi only
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Change-Id: I8bebfb2cfb68e3dad172e5547d3886526ad5e912
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Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
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---
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arch/arm/boot/dts/rk3288.dtsi | 4 +++-
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drivers/clk/rockchip/clk-rk3288.c | 4 ++--
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2 files changed, 5 insertions(+), 3 deletions(-)
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diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index 8e51132ef7e4..66962169da17 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -1052,7 +1052,7 @@
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<&cru PCLK_PERI>;
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assigned-clock-rates = <594000000>,
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<500000000>, <300000000>,
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- <150000000>, <75000000>,
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+ <0>, <75000000>,
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<300000000>, <150000000>,
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<75000000>;
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};
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@@ -1303,6 +1303,8 @@
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resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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iommus = <&vopb_mmu>;
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+ assigned-clocks = <&cru DCLK_VOP0>;
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+ assigned-clock-parents = <&cru PLL_NPLL>;
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status = "disabled";
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vopb_out: port {
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index ca6c2ad3de96..415df387a5d6 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -214,7 +214,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
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[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
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RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
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[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
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- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
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+ RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
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};
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static struct clk_div_table div_hclk_cpu_t[] = {
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@@ -429,7 +429,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK3288_CLKGATE_CON(3), 4, GFLAGS),
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- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
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+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
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RK3288_CLKGATE_CON(3), 1, GFLAGS),
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COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
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From fbefbd0989cf14e3d8f7864437a2264ab94c9b3f Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sat, 4 Aug 2018 14:51:14 +0200
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Subject: [PATCH] clk: rockchip: rk3288: use npll table to to improve HDMI
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compatibility
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Based on https://github.com/TinkerBoard/debian_kernel/commit/3d90870530b8a2901681f7b7fa598ee7381e49f3
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---
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drivers/clk/rockchip/clk-rk3288.c | 23 ++++++++++++++++++++++-
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1 file changed, 22 insertions(+), 1 deletion(-)
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index 415df387a5d6..f748a292b7f4 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -105,6 +105,27 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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{ /* sentinel */ },
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};
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+static struct rockchip_pll_rate_table rk3288_npll_rates[] = {
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+ RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32),
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+ RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
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+ RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
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+ RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
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+ RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
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+ RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
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+ RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
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+ RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
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+ RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
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+ RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
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+ RK3066_PLL_RATE(148352000, 13, 1125, 14),
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+ RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
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+ RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
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+ RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
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+ RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
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+ RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
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+ RK3066_PLL_RATE(74176000, 26, 1125, 14),
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+ { /* sentinel */ },
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+};
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+
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#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
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#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
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#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
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@@ -214,7 +235,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
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[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
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RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
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[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
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- RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
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+ RK3288_MODE_CON, 14, 9, 0, rk3288_npll_rates),
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};
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static struct clk_div_table div_hclk_cpu_t[] = {
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