rockchip: fix bootloader upgrade
This commit is contained in:
Paolo Sabatino
Igor
parent
aabae2cf60
commit
f20b2240b0
@ -65,96 +65,108 @@ CPUMIN="600000"
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CPUMAX="1900000"
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GOVERNOR="ondemand"
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write_uboot_platform() {
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# write_uboot_platform() and uboot_custom_postprocess() functions are dependent upon SOC,
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# so we declare them differently for each supported SOC. Also note that write_uboot_platform()
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# is used to install the bootloader in the proper place during live systems upgrade.
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if [[ "$BOOT_SOC" == "rk3288" ]]; then
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# Extract the Command Rate bit from existing loader.
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# Some DDR memories have issues with different Command Rate, so we
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# restore the same value after installing the new loader.
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# Note: this has to be done only on live installations (DIR variable
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# is present only during boot loader upgrade on running system)
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# while loop is only for convenient break syntax
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while [[ -n $DIR ]]; do
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write_uboot_platform() {
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# Only applicable to rk322x
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[[ "$BOOT_SOC" != "rk322x" ]] && break
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# Find the signature "a7866565" in the first 128k of the stored running image
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SIGNATURE_OFFSET=$(dd if=$2 bs=128k count=1 2> /dev/null | od -A o -w4 -tx4 | grep 'a7866565' | cut -d " " -f 1)
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# Some command failed, skip the rest
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[[ $? -ne 0 ]] && break
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# No signature found, skip the rest
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[[ -z $SIGNATURE_OFFSET ]] && break
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# Command rate bit is 16 bytes before signature
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CMD_RATE_OFFSET=$(($SIGNATURE_OFFSET - 16))
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CR_BYTE=$(od -A n -t dI -j $CMD_RATE_OFFSET -N 1 $2)
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# No command rate byte for some reason, skip the rest
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[[ -z $CR_BYTE ]] && break
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# Invalid command rate byte (should be 0 or 1), skip the rest
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[[ "$CR_BYTE" -ne 0 && "$CR_BYTE" -ne 1 ]] && break
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# Proceed patching u-boot-rk322x-with-spl.bin, do find the
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# cr bit there too to verify that the position of the CR bit is right
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SIGNATURE_OFFSET=$(dd if=$1/u-boot-rk322x-with-spl.bin bs=128k count=1 2> /dev/null | od -A o -w4 -tx4 | grep 'a7866565' | cut -d " " -f 1)
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# Some command failed, skip the rest
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[[ $? -ne 0 ]] && break
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# No signature found, skip the rest
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[[ -z $SIGNATURE_OFFSET ]] && break
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# Command rate bit is 16 bytes before signature
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CMD_RATE_OFFSET=$(($SIGNATURE_OFFSET - 16))
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DST_BYTE=$(od -A n -t dI -j $CMD_RATE_OFFSET -N 1 $1/u-boot-rk322x-with-spl.bin)
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# Verify command rate byte is 0 or 1
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[[ "$DST_BYTE" -ne 0 && "$DST_BYTE" -ne 1 ]] && break
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# Patch the file
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[[ "$CR_BYTE" -eq 0 ]] && HEX_CR="\x00"
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[[ "$CR_BYTE" -eq 1 ]] && HEX_CR="\x01"
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echo -e $HEX_CR | dd of=$1/u-boot-rk322x-with-spl.bin bs=1 seek=$CMD_RATE_OFFSET count=1 conv=notrunc > /dev/null 2>&1
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# always break the while loop
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break
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done
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if [[ "$BOOT_SOC" == "rk3288" ]]; then
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UBOOT_SRC="u-boot-rockchip-with-spl.bin"
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elif [[ "$BOOT_SOC" == "rk322x" ]]; then
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UBOOT_SRC="u-boot-rk322x-with-spl.bin"
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fi
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dd if=/dev/zero of=$2 bs=32k count=63 seek=1 status=noxfer > /dev/null 2>&1
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dd if=$1/$UBOOT_SRC of=$2 bs=32k seek=1 conv=notrunc
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dd if=/dev/zero of=$2 bs=32k count=63 seek=1 status=noxfer > /dev/null 2>&1
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dd if=$1/$UBOOT_SRC of=$2 bs=32k seek=1 conv=notrunc
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}
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}
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uboot_custom_postprocess() {
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if [[ "$BOOT_SOC" == "rk3288" ]]; then
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uboot_custom_postprocess() {
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# xt-q8l-v10 requires the original DDR init blob because u-boot does not support LPDDR2 initialization
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# for rk3288 SoC (binary is in sources/rkbin-tools/rk32 path). U-boot is configured to produce a TPL
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# which is thrown away. SPL does some more initial configurations, expecially pinmux for power hold,
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# so reset works more reliably. U-boot image is set to be at sector 0x200 on the eMMC/SD,
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# so we burn it 0x200-0x40 because of the rockchip 0x40 sectors offset.
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if [[ $BOARD == xt-q8l-v10 ]]; then
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if [[ "$BOARD" == "xt-q8l-v10" ]]; then
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run_host_command_logged tools/mkimage -n rk3288 -T rksd -d $SRC/cache/sources/rkbin-tools/rk32/rk3288_ddr_400MHz_v1.08.bin u-boot-rockchip-with-spl.bin
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else
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run_host_command_logged tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin u-boot-rockchip-with-spl.bin
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fi
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cat spl/u-boot-spl-dtb.bin >> u-boot-rockchip-with-spl.bin
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dd if=u-boot-dtb.img of=u-boot-rockchip-with-spl.bin seek=$((0x200 - 0x40)) conv=notrunc
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run_host_command_logged cat spl/u-boot-spl-dtb.bin >> u-boot-rockchip-with-spl.bin
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run_host_command_logged dd if=u-boot-dtb.img of=u-boot-rockchip-with-spl.bin seek=$((0x200 - 0x40)) conv=notrunc
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elif [[ "$BOOT_SOC" == "rk322x" ]]; then
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}
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elif [[ "$BOOT_SOC" == "rk322x" ]]; then
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write_uboot_platform() {
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# Extract the Command Rate bit from existing loader.
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# Some DDR memories have issues with different Command Rate, so we
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# restore the same value after installing the new loader.
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# Note: this has to be done only on live installations (DIR variable
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# is present only during boot loader upgrade on running system)
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# while loop is only for convenient break syntax
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while [[ -n $DIR ]]; do
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# Only applicable to rk322x
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[[ "$BOOT_SOC" != "rk322x" ]] && break
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# Find the signature "a7866565" in the first 128k of the stored running image
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SIGNATURE_OFFSET=$(dd if=$2 bs=128k count=1 2> /dev/null | od -A o -w4 -tx4 | grep 'a7866565' | cut -d " " -f 1)
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# Some command failed, skip the rest
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[[ $? -ne 0 ]] && break
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# No signature found, skip the rest
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[[ -z $SIGNATURE_OFFSET ]] && break
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# Command rate bit is 16 bytes before signature
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CMD_RATE_OFFSET=$(($SIGNATURE_OFFSET - 16))
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CR_BYTE=$(od -A n -t dI -j $CMD_RATE_OFFSET -N 1 $2)
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# No command rate byte for some reason, skip the rest
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[[ -z $CR_BYTE ]] && break
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# Invalid command rate byte (should be 0 or 1), skip the rest
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[[ "$CR_BYTE" -ne 0 && "$CR_BYTE" -ne 1 ]] && break
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# Proceed patching u-boot-rk322x-with-spl.bin, do find the
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# cr bit there too to verify that the position of the CR bit is right
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SIGNATURE_OFFSET=$(dd if=$1/u-boot-rk322x-with-spl.bin bs=128k count=1 2> /dev/null | od -A o -w4 -tx4 | grep 'a7866565' | cut -d " " -f 1)
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# Some command failed, skip the rest
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[[ $? -ne 0 ]] && break
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# No signature found, skip the rest
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[[ -z $SIGNATURE_OFFSET ]] && break
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# Command rate bit is 16 bytes before signature
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CMD_RATE_OFFSET=$(($SIGNATURE_OFFSET - 16))
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DST_BYTE=$(od -A n -t dI -j $CMD_RATE_OFFSET -N 1 $1/u-boot-rk322x-with-spl.bin)
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# Verify command rate byte is 0 or 1
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[[ "$DST_BYTE" -ne 0 && "$DST_BYTE" -ne 1 ]] && break
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# Patch the file
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[[ "$CR_BYTE" -eq 0 ]] && HEX_CR="\x00"
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[[ "$CR_BYTE" -eq 1 ]] && HEX_CR="\x01"
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echo -e $HEX_CR | dd of=$1/u-boot-rk322x-with-spl.bin bs=1 seek=$CMD_RATE_OFFSET count=1 conv=notrunc > /dev/null 2>&1
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# always break the while loop
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break
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done
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UBOOT_SRC="u-boot-rk322x-with-spl.bin"
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dd if=/dev/zero of=$2 bs=32k count=63 seek=1 status=noxfer > /dev/null 2>&1
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dd if=$1/$UBOOT_SRC of=$2 bs=32k seek=1 conv=notrunc
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}
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uboot_custom_postprocess() {
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# We use the rockchip proprietary blob to initialize memory chips
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# instead of letting u-boot doing the job. Such devices, like xt-mx4vr-v01, have DDR2
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@ -172,9 +184,9 @@ uboot_custom_postprocess() {
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run_host_command_logged cat spl/u-boot-spl.bin ">>" u-boot-rk322x-with-spl.bin
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run_host_command_logged dd if=u-boot.itb of=u-boot-rk322x-with-spl.bin seek=$((0x200 - 0x40)) conv=notrunc
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fi
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}
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}
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fi
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family_tweaks() {
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