Update 92-mvebu-gpio-remove-hardcoded-timer-assignment.patch for lk5.12
Tested with helios4, pwm working on both channels
This commit is contained in:
Heisath
parent
d787b30311
commit
ebc3997e4b
@ -1,6 +1,6 @@
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From e4728fcf779c37d1bcbd4b6505c9b40d4bb9ff48 Mon Sep 17 00:00:00 2001
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From: Heisath <jannis@imserv.org>
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Date: Mon, 22 Feb 2021 12:24:54 +0100
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Date: Thu, 03 Jun 2021 10:56:53 +0200
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Subject: [PATCH] Removes the hardcoded timer assignment of timers to pwm controllers
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This allows to use more than one pwm per gpio bank.
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@ -8,14 +8,12 @@ Original patch by helios4 team, updated to work on LK5.11+
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Signed-off-by: Heisath <jannis@imserv.org>
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---
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drivers/gpio/gpio-mvebu.c | 198 +++++++++++++++++++++++++++-----------
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1 file changed, 144 insertions(+), 54 deletions(-)
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diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
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index 3a19b4140..195b685de 100644
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index bad399e3f..d3fdaf177 100644
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--- a/drivers/gpio/gpio-mvebu.c
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+++ b/drivers/gpio/gpio-mvebu.c
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@@ -92,20 +92,41 @@
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@@ -97,21 +97,42 @@
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#define MVEBU_MAX_GPIO_PER_BANK 32
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@ -28,57 +26,57 @@ index 3a19b4140..195b685de 100644
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+
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+struct mvebu_pwmchip {
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struct regmap *regs;
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- unsigned long clk_rate;
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+ unsigned long clk_rate;
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+ spinlock_t lock;
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+ bool in_use;
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+
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+ /* Used to preserve GPIO/PWM registers across suspend/resume */
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+ u32 blink_on_duration;
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+ u32 blink_off_duration;
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+};
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+
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+struct mvebu_pwm_chip_drv {
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+ enum mvebu_pwm_ctrl ctrl;
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struct gpio_desc *gpiod;
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u32 offset;
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unsigned long clk_rate;
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- struct gpio_desc *gpiod;
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- struct pwm_chip chip;
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- spinlock_t lock;
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+ bool master;
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+};
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+
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+struct mvebu_pwm {
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+ struct pwm_chip chip;
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struct mvebu_gpio_chip *mvchip;
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+ struct mvebu_pwmchip controller;
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+ enum mvebu_pwm_ctrl default_counter;
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spinlock_t lock;
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- struct mvebu_gpio_chip *mvchip;
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+ bool in_use;
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/* Used to preserve GPIO/PWM registers across suspend/resume */
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u32 blink_select;
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- u32 blink_on_duration;
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- u32 blink_off_duration;
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- u32 blink_select;
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u32 blink_on_duration;
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u32 blink_off_duration;
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};
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+static struct mvebu_pwmchip *mvebu_pwm_list[MVEBU_PWM_CTRL_MAX];
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+struct mvebu_pwm_chip_drv {
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+ enum mvebu_pwm_ctrl ctrl;
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+ struct gpio_desc *gpiod;
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+ bool master;
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+};
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+
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+struct mvebu_pwm {
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+ struct pwm_chip chip;
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+ struct mvebu_gpio_chip *mvchip;
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+ struct mvebu_pwmchip controller;
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+ enum mvebu_pwm_ctrl default_counter;
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+
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+ /* Used to preserve GPIO/PWM registers across suspend/resume */
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+ u32 blink_select;
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+};
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+
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+static struct mvebu_pwmchip *mvebu_pwm_list[MVEBU_PWM_CTRL_MAX];
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+
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struct mvebu_gpio_chip {
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struct gpio_chip chip;
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struct regmap *regs;
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@@ -282,12 +303,12 @@ mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
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@@ -288,12 +309,12 @@ mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
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* Functions returning offsets of individual registers for a given
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* PWM controller.
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*/
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-static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
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+static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwmchip *mvpwm)
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{
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return PWM_BLINK_ON_DURATION_OFF;
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return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
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}
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-static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
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+static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwmchip *mvpwm)
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{
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return PWM_BLINK_OFF_DURATION_OFF;
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return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
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}
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@@ -647,39 +668,84 @@ static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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@@ -653,39 +674,84 @@ static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
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struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
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struct gpio_desc *desc;
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@ -86,12 +84,9 @@ index 3a19b4140..195b685de 100644
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unsigned long flags;
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int ret = 0;
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+ struct mvebu_pwm_chip_drv *chip_data;
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+
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+ spin_lock_irqsave(&mvpwm->controller.lock, flags);
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- spin_lock_irqsave(&mvpwm->lock, flags);
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+ regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
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+ &mvchip->blink_en_reg);
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+ spin_lock_irqsave(&mvpwm->controller.lock, flags);
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- if (mvpwm->gpiod) {
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+ if (pwm->chip_data || (mvchip->blink_en_reg & BIT(pwm->hwpwm))) {
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@ -106,13 +101,14 @@ index 3a19b4140..195b685de 100644
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- goto out;
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- }
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+ goto out;
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+ }
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- mvpwm->gpiod = desc;
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+ }
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+
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+
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+
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+ desc = gpiochip_request_own_desc(&mvchip->chip,
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+ pwm->hwpwm, "mvebu-pwm",
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+ GPIO_ACTIVE_HIGH,
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+ GPIOD_OUT_LOW);
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+ pwm->hwpwm, "mvebu-pwm",
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+ GPIO_ACTIVE_HIGH,
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+ GPIOD_OUT_LOW);
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+
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+ if (IS_ERR(desc)) {
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+ ret = PTR_ERR(desc);
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@ -120,28 +116,29 @@ index 3a19b4140..195b685de 100644
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+ }
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+
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+ ret = gpiod_direction_output(desc, 0);
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+ if (ret) {
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+ if (ret) {
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+ gpiochip_free_own_desc(desc);
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+ goto out;
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}
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+
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+ }
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- mvpwm->gpiod = desc;
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+ chip_data = kzalloc(sizeof(struct mvebu_pwm_chip_drv), GFP_KERNEL);
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+ if (!chip_data) {
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+ gpiochip_free_own_desc(desc);
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+ ret = -ENOMEM;
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+ goto out;
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+ }
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+
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+ }
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+
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+ for (id = MVEBU_PWM_CTRL_SET_A; id < MVEBU_PWM_CTRL_MAX; id++) {
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+ if (!mvebu_pwm_list[id]->in_use) {
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+ chip_data->ctrl = id;
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+ chip_data->master = true;
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+ chip_data->ctrl = id;
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+ chip_data->master = true;
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+ mvebu_pwm_list[id]->in_use = true;
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+ break;
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+ }
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+ }
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}
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+
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+ if (!chip_data->master)
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+ if (!chip_data->master)
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+ chip_data->ctrl = mvpwm->default_counter;
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+
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+ regmap_update_bits(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
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@ -149,7 +146,7 @@ index 3a19b4140..195b685de 100644
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+
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+ chip_data->gpiod = desc;
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+ pwm->chip_data = chip_data;
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+
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+
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+ regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
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+ &mvpwm->blink_select);
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+
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@ -173,6 +170,7 @@ index 3a19b4140..195b685de 100644
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+ if (chip_data->master)
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+ mvebu_pwm_list[chip_data->ctrl]->in_use = false;
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+
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+
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+ gpiochip_free_own_desc(chip_data->gpiod);
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+ kfree(chip_data);
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+ pwm->chip_data = NULL;
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@ -180,7 +178,7 @@ index 3a19b4140..195b685de 100644
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}
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static void mvebu_pwm_get_state(struct pwm_chip *chip,
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@@ -687,16 +753,23 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
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@@ -693,29 +759,36 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
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struct pwm_state *state) {
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struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
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@ -201,26 +199,28 @@ index 3a19b4140..195b685de 100644
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- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
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+ regmap_read(controller->regs, mvebu_pwmreg_blink_on_duration(controller), &u);
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val = (unsigned long long) u * NSEC_PER_SEC;
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- do_div(val, mvpwm->clk_rate);
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+ do_div(val, controller->clk_rate);
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if (val > UINT_MAX)
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state->duty_cycle = UINT_MAX;
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else if (val)
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@@ -705,10 +778,10 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
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state->duty_cycle = 1;
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/* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
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if (u > 0)
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val = u;
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else
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val = UINT_MAX + 1ULL;
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state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
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- mvpwm->clk_rate);
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+ controller->clk_rate);
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val = (unsigned long long) u; /* on duration */
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- regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
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+ regmap_read(controller->regs, mvebu_pwmreg_blink_off_duration(controller), &u);
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val += (unsigned long long) u; /* period = on + off duration */
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val *= NSEC_PER_SEC;
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- do_div(val, mvpwm->clk_rate);
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+ do_div(val, controller->clk_rate);
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if (val > UINT_MAX)
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state->period = UINT_MAX;
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else if (val)
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@@ -722,19 +795,27 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
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/* period = on + off duration */
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if (u > 0)
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val += u;
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else
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val += UINT_MAX + 1ULL;
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- state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
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+ state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, controller->clk_rate);
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regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
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if (u)
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@@ -723,19 +796,26 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
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else
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state->enabled = false;
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@ -245,21 +245,20 @@ index 3a19b4140..195b685de 100644
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+ else
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+ controller = &mvpwm->controller;
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+
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+
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+ val = (unsigned long long) controller->clk_rate * state->duty_cycle;
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do_div(val, NSEC_PER_SEC);
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if (val > UINT_MAX)
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if (val > UINT_MAX + 1ULL)
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return -EINVAL;
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@@ -743,7 +824,7 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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@@ -750,7 +830,7 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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else
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on = 1;
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- val = (unsigned long long) mvpwm->clk_rate *
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+ val = (unsigned long long) controller->clk_rate *
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(state->period - state->duty_cycle);
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- val = (unsigned long long) mvpwm->clk_rate * state->period;
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+ val = (unsigned long long) controller->clk_rate * state->period;
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do_div(val, NSEC_PER_SEC);
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if (val > UINT_MAX)
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@@ -753,16 +834,16 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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val -= on;
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if (val > UINT_MAX + 1ULL)
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@@ -762,16 +842,16 @@ static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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else
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off = 1;
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@ -280,7 +279,7 @@ index 3a19b4140..195b685de 100644
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return 0;
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}
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@@ -778,25 +859,27 @@ static const struct pwm_ops mvebu_pwm_ops = {
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@@ -787,25 +867,27 @@ static const struct pwm_ops mvebu_pwm_ops = {
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static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
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{
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struct mvebu_pwm *mvpwm = mvchip->mvpwm;
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@ -316,46 +315,116 @@ index 3a19b4140..195b685de 100644
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}
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static int mvebu_pwm_probe(struct platform_device *pdev,
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@@ -807,6 +890,7 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
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struct mvebu_pwm *mvpwm;
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@@ -817,26 +899,20 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
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void __iomem *base;
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u32 offset;
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u32 set;
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+ enum mvebu_pwm_ctrl ctrl_set;
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if (!of_device_is_compatible(mvchip->chip.of_node,
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"marvell,armada-370-gpio"))
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@@ -828,12 +912,16 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
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* Use set A for lines of GPIO chip with id 0, B for GPIO chip
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* with id 1. Don't allow further GPIO chips to be used for PWM.
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*/
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- if (id == 0)
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+ if (id == 0) {
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set = 0;
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- else if (id == 1)
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+ ctrl_set = MVEBU_PWM_CTRL_SET_A;
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+ } else if (id == 1) {
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set = U32_MAX;
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- else
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+ ctrl_set = MVEBU_PWM_CTRL_SET_B;
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+ } else {
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return -EINVAL;
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+ }
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- if (of_device_is_compatible(mvchip->chip.of_node,
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- "marvell,armada-370-gpio")) {
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- /*
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- * There are only two sets of PWM configuration registers for
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- * all the GPIO lines on those SoCs which this driver reserves
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- * for the first two GPIO chips. So if the resource is missing
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- * we can't treat it as an error.
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- */
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- if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
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- return 0;
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- offset = 0;
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- } else if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
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- int ret = of_property_read_u32(dev->of_node,
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- "marvell,pwm-offset", &offset);
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- if (ret < 0)
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- return 0;
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- } else {
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+ if (!of_device_is_compatible(mvchip->chip.of_node,
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+ "marvell,armada-370-gpio"))
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+ return 0;
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+
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regmap_write(mvchip->regs,
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GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
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+ /*
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+ * There are only two sets of PWM configuration registers for
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+ * all the GPIO lines on those SoCs which this driver reserves
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+ * for the first two GPIO chips. So if the resource is missing
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+ * we can't treat it as an error.
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+ */
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+ if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
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return 0;
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- }
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@@ -847,13 +935,13 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
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if (IS_ERR(base))
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return PTR_ERR(base);
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if (IS_ERR(mvchip->clk))
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return PTR_ERR(mvchip->clk);
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@@ -844,54 +920,39 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
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mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
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if (!mvpwm)
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return -ENOMEM;
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+
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mvchip->mvpwm = mvpwm;
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mvpwm->mvchip = mvchip;
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- mvpwm->offset = offset;
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+
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+
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+ base = devm_platform_ioremap_resource_byname(pdev, "pwm");
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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- mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
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- if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
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- mvpwm->regs = mvchip->regs;
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+ mvpwm->controller.regs = devm_regmap_init_mmio(&pdev->dev, base,
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&mvebu_gpio_regmap_config);
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- if (IS_ERR(mvpwm->regs))
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- return PTR_ERR(mvpwm->regs);
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+ &mvebu_gpio_regmap_config);
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+ if (IS_ERR(mvpwm->controller.regs))
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+ return PTR_ERR(mvpwm->controller.regs);
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- switch (mvchip->offset) {
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- case AP80X_GPIO0_OFF_A8K:
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- case CP11X_GPIO0_OFF_A8K:
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- /* Blink counter A */
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- set = 0;
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- break;
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- case CP11X_GPIO1_OFF_A8K:
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- /* Blink counter B */
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- set = U32_MAX;
|
||||
- mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
|
||||
- break;
|
||||
- default:
|
||||
- return -EINVAL;
|
||||
- }
|
||||
+ /*
|
||||
+ * Use set A for lines of GPIO chip with id 0, B for GPIO chip
|
||||
+ * with id 1. Don't allow further GPIO chips to be used for PWM.
|
||||
+ */
|
||||
+ if (id == 0) {
|
||||
+ set = 0;
|
||||
+ ctrl_set = MVEBU_PWM_CTRL_SET_A;
|
||||
+ } else if (id == 1) {
|
||||
+ set = U32_MAX;
|
||||
+ ctrl_set = MVEBU_PWM_CTRL_SET_B;
|
||||
} else {
|
||||
- base = devm_platform_ioremap_resource_byname(pdev, "pwm");
|
||||
- if (IS_ERR(base))
|
||||
- return PTR_ERR(base);
|
||||
-
|
||||
- mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
|
||||
- &mvebu_gpio_regmap_config);
|
||||
- if (IS_ERR(mvpwm->regs))
|
||||
- return PTR_ERR(mvpwm->regs);
|
||||
-
|
||||
- /*
|
||||
- * Use set A for lines of GPIO chip with id 0, B for GPIO chip
|
||||
- * with id 1. Don't allow further GPIO chips to be used for PWM.
|
||||
- */
|
||||
- if (id == 0)
|
||||
- set = 0;
|
||||
- else if (id == 1)
|
||||
- set = U32_MAX;
|
||||
- else
|
||||
- return -EINVAL;
|
||||
+ return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_write(mvchip->regs,
|
||||
GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
|
||||
|
||||
- mvpwm->clk_rate = clk_get_rate(mvchip->clk);
|
||||
- if (!mvpwm->clk_rate) {
|
||||
+ mvpwm->controller.clk_rate = clk_get_rate(mvchip->clk);
|
||||
@ -363,17 +432,15 @@ index 3a19b4140..195b685de 100644
|
||||
dev_err(dev, "failed to get clock rate\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
@@ -869,7 +957,9 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
|
||||
@@ -907,7 +968,10 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
|
||||
*/
|
||||
mvpwm->chip.base = -1;
|
||||
|
||||
- spin_lock_init(&mvpwm->lock);
|
||||
+ spin_lock_init(&mvpwm->controller.lock);
|
||||
+
|
||||
+ mvpwm->default_counter = ctrl_set;
|
||||
+ mvebu_pwm_list[ctrl_set] = &mvpwm->controller;
|
||||
|
||||
return pwmchip_add(&mvpwm->chip);
|
||||
}
|
||||
--
|
||||
Created with Armbian build tools https://github.com/armbian/build
|
||||
|
||||
Loading…
Reference in New Issue
Block a user