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Few Espressobin fixes for 4.13.x SD card is still unrecognized, but is possible to boot from USB. It crashes with attached mPCI card ... need to update atf and uboot once in the future

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This commit is contained in:
Igor Pecovnik 2017-09-24 22:44:50 +02:00
parent e3f10c4c02
commit e886835232
9 changed files with 230 additions and 137 deletions
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6
config/bootscripts/boot-espressobin.cmd
View File

@ -1,7 +1,7 @@
setenv boot_interface mmc
setenv image_name boot/Image
setenv fdt_name boot/dtb/marvell/armada-3720-community.dtb
setenv fdt_name_a boot/dtb/marvell/armada-3720-community.dtb
setenv fdt_name_b boot/dtb/marvell/armada-3720-espressobin.dtb
setenv fdt_high "0xffffffffffffffff"
setenv rootdev "/dev/mmcblk0p1"
setenv rootfstype "ext4"
@ -9,5 +9,5 @@ setenv verbosity "1"
setenv initrd_addr "0x1100000"
setenv initrd_image "boot/uInitrd"
setenv ethaddr "F0:AD:4E:03:64:7F"
setenv bootcmd 'mmc dev 0; ext4load mmc 0:1 $kernel_addr $image_name;ext4load mmc 0:1 $initrd_addr $initrd_image; ext4load mmc 0:1 $fdt_addr $fdt_name;setenv bootargs $console root=$rootdev rw rootwait; booti $kernel_addr $initrd_addr $fdt_addr'
setenv bootcmd 'mmc dev 0; ext4load mmc 0:1 $kernel_addr $image_name;ext4load mmc 0:1 $initrd_addr $initrd_image; ext4load mmc 0:1 $fdt_addr $fdt_name_a;ext4load mmc 0:1 $fdt_addr $fdt_name_b;setenv bootargs $console root=$rootdev rw rootwait; booti $kernel_addr $initrd_addr $fdt_addr'

72
patch/kernel/mvebu64-next/0005-arm64-dts-marvell-Enable-second-SDHCI-controller-in-.patch.disabled
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@ -1,72 +0,0 @@
From aff7d41d285c04f5990247660c860e30029f72b2 Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Tue, 23 May 2017 16:11:40 +0300
Subject: [PATCH 05/11] arm64: dts: marvell: Enable second SDHCI controller in
Armada 37xx
The Armada 37xx SoCs has 2 SDHCI interfaces. This patch adds the second
one.
Moreover, the Armada 37xx DB v2 board populates the 2 SDHCI interfaces.
The second interface is using pluggable module that can either
have an SD connector or eMMC on it.
This patch adds support for SD module in the device DT.
[ gregory.clement@free-electrons.com:
- Add more detail in commit log
- Sort the dt node in address order
- Document the SD slot in the dts ]
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 9 +++++++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index a89855f57091..6a0abd7a5349 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -113,6 +113,15 @@
status = "okay";
};
+/* SD slot module on CON14(V2.0)/CON15(V1.4) */
+&sdhci1 {
+ wp-inverted;
+ cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ marvell,pad-type = "sd";
+ status = "okay";
+};
+
&spi0 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index f4deb8cd11c6..a78195b4ef7a 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -293,6 +293,17 @@
};
};
+ sdhci1: sdhci@d0000 {
+ compatible = "marvell,armada-3700-sdhci",
+ "marvell,sdhci-xenon";
+ reg = <0xd0000 0x300>,
+ <0x1e808 0x4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 0>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
sdhci0: sdhci@d8000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";
--
2.13.3

51
patch/kernel/mvebu64-next/0006-PCI-aardvark-fix-logic-in-PCI-configuration-read-wri.patch Normal file
View File

@ -0,0 +1,51 @@
From 19f028017f93b19bd4142840a0714fc3b5c447a1 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 8 Sep 2017 11:53:42 +0200
Subject: [PATCH 06/12] PCI: aardvark: fix logic in PCI configuration
read/write functions
The PCI configuration space read/write functions were special casing
the situation where PCI_SLOT(devfn) != 0, and returned
PCIBIOS_DEVICE_NOT_FOUND in this case.
However, will this is what is intended for the root bus, it is not
intended for the child busses, as it prevents discovering devices with
PCI_SLOT(x) != 0. Therefore, we return PCIBIOS_DEVICE_NOT_FOUND only
if we're on the root bus.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 5fb9b620ac78..582d75f864e3 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -441,7 +441,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
u32 reg;
int ret;
- if (PCI_SLOT(devfn) != 0) {
+ if ((bus->number == pcie->root_bus_nr) && (PCI_SLOT(devfn) != 0)) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -495,7 +495,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int offset;
int ret;
- if (PCI_SLOT(devfn) != 0)
+ if ((bus->number == pcie->root_bus_nr) && (PCI_SLOT(devfn) != 0))
return PCIBIOS_DEVICE_NOT_FOUND;
if (where % size)
--
2.14.1

38
patch/kernel/mvebu64-next/0007-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_.patch Normal file
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@ -0,0 +1,38 @@
From e692c4478048fdcc01c939f28e9801aebdd622d3 Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 8 Sep 2017 11:53:43 +0200
Subject: [PATCH 07/12] PCI: aardvark: set PIO_ADDR_LS correctly in
advk_pcie_rd_conf()
When setting the PIO_ADDR_LS register during a configuration read, we
were properly passing the device number, function number and register
number, but not the bus number, causing issues when reading the
configuration of PCIe devices.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 582d75f864e3..68ff10e17c74 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -460,7 +460,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
+ reg = PCIE_CONF_ADDR(bus->number, devfn, where);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
--
2.14.1

54
patch/kernel/mvebu64-next/0010-pci-aardvard-set-host-and-device-to-the-same-MAX-pay.patch → patch/kernel/mvebu64-next/0008-PCI-aardvark-set-host-and-device-to-the-same-MAX-pay.patch
View File

@ -1,37 +1,55 @@
From dda187271721fbc30329d56fd68034c54e304a44 Mon Sep 17 00:00:00 2001
From 6ce52078a28550c7103b79b2b26de08185035bda Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 24 Mar 2017 20:52:30 +0800
Subject: [PATCH 10/11] pci: aardvard: set host and device to the same MAX
Date: Fri, 8 Sep 2017 11:53:44 +0200
Subject: [PATCH 08/12] PCI: aardvark: set host and device to the same MAX
payload size
Since the Aardvard does not implement PCIe root bus, the Linux PCIe
framework will not align the MAX payload size between host and device
for it.
This patch sets host and device to the same MAX payload size in Aardvard
PCIe driver.
Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
subsystem will not align the MAX payload size between the host and the
device. This patch ensures that the host and device have the same MAX
payload size, fixing a number of problems with various PCIe devices.
Change-Id: I3979397b3af98911c067f7ad384922aa3f05497f
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37927
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/pci/host/pci-aardvark.c | 56 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 10154dcf219b..0407c8cb89fb 100644
index 68ff10e17c74..e361c673732f 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -32,6 +32,7 @@
@@ -30,8 +30,10 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
+#define PCIE_CORE_MPS_UNIT_BYTE 128
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
#define PCIE_CORE_LINK_TRAINING BIT(5)
@@ -886,6 +887,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
@@ -298,7 +300,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
@@ -880,6 +883,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
return err;
}
@ -90,7 +108,7 @@ index 10154dcf219b..0407c8cb89fb 100644
static int advk_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -948,6 +1001,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
@@ -951,6 +1006,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
@ -101,5 +119,5 @@ index 10154dcf219b..0407c8cb89fb 100644
return 0;
}
--
2.13.3
2.14.1

44
patch/kernel/mvebu64-next/0011-fix-pcie-aardvark-correct-the-default-MAX-payload-si.patch
View File

@ -1,44 +0,0 @@
From 100881d53b53c3c6691a3f3b4ddfc88d738c753b Mon Sep 17 00:00:00 2001
From: Victor Gu <xigu@marvell.com>
Date: Fri, 24 Mar 2017 20:41:55 +0800
Subject: [PATCH 11/11] fix: pcie: aardvark: correct the default MAX payload
size
The previous PCIe MAX payload field is set to 7 which is undefined
value according to functional specification.
The default PICe host controller MAX payload size should be
set to 512 bytes according to specification.
Change-Id: I8fa4868ad251f2582d58ed588e570c43aa8b24b9
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37926
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Evan Wang <xswang@marvell.com>
---
drivers/pci/host/pci-aardvark.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 0407c8cb89fb..cac1558b8d3b 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -30,6 +30,7 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
#define PCIE_CORE_MPS_UNIT_BYTE 128
@@ -300,7 +301,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
--
2.13.3

39
patch/kernel/mvebu64-next/0012-PCI-aardvark-define-IRQ-related-hooks-in-pci_host_br.patch Normal file
View File

@ -0,0 +1,39 @@
From e1387e57b57b39a22d626d6f6f8ae5e6fa1a4567 Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Fri, 8 Sep 2017 11:53:48 +0200
Subject: [PATCH 12/12] PCI: aardvark: define IRQ related hooks in
pci_host_bridge
Commit 769b461fc0c0 ("arm64: PCI: Drop DT IRQ allocation from
pcibios_alloc_irq()") was assuming all PCI host controller drivers had
been converted to use ->map_irq(), but that wasn't the case:
pci-aardvark had not been converted. Due to this, it broke the support
for legacy PCI interrupts when using the pci-aardvark driver (used on
Marvell Armada 3720 platforms).
In order to fix this, we make sure the ->map_irq and ->swizzle_irq
fields of pci_host_bridge are properly filled in.
Fixes: 769b461fc0c0 ("arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v4.13+
---
drivers/pci/host/pci-aardvark.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 6d6a2ae35481..f682650bf037 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -999,6 +999,8 @@ static int advk_pcie_probe(struct platform_device *pdev)
bridge->sysdata = pcie;
bridge->busnr = 0;
bridge->ops = &advk_pcie_ops;
+ bridge->map_irq = of_irq_parse_and_map_pci;
+ bridge->swizzle_irq = pci_common_swizzle;
ret = pci_scan_root_bus_bridge(bridge);
if (ret < 0) {
--
2.14.1

13
patch/kernel/mvebu64-next/set-default-target-to-Image.patch Normal file
View File

@ -0,0 +1,13 @@
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index f839ecd9..cd276162 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -103,7 +103,7 @@ core-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
# Default target when executing plain make
boot := arch/arm64/boot
-KBUILD_IMAGE := $(boot)/Image.gz
+KBUILD_IMAGE := $(boot)/Image
KBUILD_DTBS := dtbs
all: Image.gz $(KBUILD_DTBS)

50
patch/kernel/mvebu64-next/zImage_to_Image.patch Normal file
View File

@ -0,0 +1,50 @@
diff --git a/scripts/package/builddeb b/scripts/package/builddeb
index 0f8de20..3a39d73 100755
--- a/scripts/package/builddeb
+++ b/scripts/package/builddeb
@@ -251,7 +251,7 @@ done
##
sed -e "s/set -e//g" -i $tmpdir/DEBIAN/postinst
sed -e "s/exit 0//g" -i $tmpdir/DEBIAN/postinst
-cat >> $tmpdir/DEBIAN/postinst <<EOT
+cat >> $tmpdir/DEBIAN/postinst <<EOT
if [ "\$(grep nand /proc/partitions)" != "" ] && [ "\$(grep mmc /proc/partitions)" = "" ]; then
mkimage -A arm -O linux -T kernel -C none -a "0x40008000" -e "0x40008000" -n "Linux kernel" -d /$installed_image_path /boot/uImage > /dev/null 2>&1
cp /boot/uImage /tmp/uImage
@@ -260,7 +260,7 @@ mountpoint -q /boot || mount /boot
cp /tmp/uImage /boot/uImage
rm -f /$installed_image_path
else
-ln -sf $(basename $installed_image_path) /boot/zImage > /dev/null 2>&1 || mv /$installed_image_path /boot/zImage
+ln -sf $(basename $installed_image_path) /boot/Image > /dev/null 2>&1 || mv /$installed_image_path /boot/Image
fi
touch /boot/.next
exit 0
@@ -270,7 +270,7 @@ EOT
##
sed -e "s/set -e//g" -i $tmpdir/DEBIAN/preinst
sed -e "s/exit 0//g" -i $tmpdir/DEBIAN/preinst
-cat >> $tmpdir/DEBIAN/preinst <<EOT
+cat >> $tmpdir/DEBIAN/preinst <<EOT
# exit if we are running chroot
if [ "\$(stat -c %d:%i /)" != "\$(stat -c %d:%i /proc/1/root/.)" ]; then exit 0; fi
@@ -286,14 +286,14 @@ for file in /dev/* ; do
done
bootfstype=\$(blkid -s TYPE -o value \$boot_partition)
-if [ "\$bootfstype" = "vfat" ]; then
-umount /boot;
-rm -f /boot/System.map* /boot/config* /boot/vmlinuz* /boot/zImage /boot/uImage
+if [ "\$bootfstype" = "vfat" ]; then
+umount /boot;
+rm -f /boot/System.map* /boot/config* /boot/vmlinuz* /boot/Image /boot/uImage
fi
}
mountpoint -q /boot && check_and_unmount
EOT
-echo "exit 0" >> $tmpdir/DEBIAN/preinst
+echo "exit 0" >> $tmpdir/DEBIAN/preinst
# Try to determine maintainer and email values
if [ -n "$DEBEMAIL" ]; then