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Split missing H3 boards u-boot patch

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Use NanoPi M1 u-boot config from upstream
This will require patching kernel to add M1 DT file
This commit is contained in:
zador-blood-stained 2016-12-01 22:18:51 +03:00
parent 6bd659e566
commit e84d47fc3d
13 changed files with 121 additions and 246 deletions
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4
config/boards/nanopiair.conf
View File

@ -1,8 +1,8 @@
# H3 quad core 512MB SoC Headless WiFi/BT
BOARD_NAME="NanoPi Air"
LINUXFAMILY=sun8i
BOOTCONFIG=FriendlyARM_NanoPi_Air_defconfig
MODULES="#gpio-sunxi #w1-sunxi #w1-gpio #w1-therm #sunxi-cir hci_uart rfcomm hidp dhd g_serial"
BOOTCONFIG="nanopi_air_defconfig"
MODULES="#w1-sunxi #w1-gpio #w1-therm #sunxi-cir hci_uart rfcomm hidp dhd g_serial"
MODULES_NEXT="brcmfmac"
CPUMIN=240000
CPUMAX=912000

2
config/boards/nanopim1.conf
View File

@ -1,7 +1,7 @@
# H3 quad core 1Gb SoC
BOARD_NAME="NanoPi M1"
LINUXFAMILY=sun8i
BOOTCONFIG=FriendlyARM_NanoPi_M1_defconfig
BOOTCONFIG="nanopi_m1_defconfig"
MODULES="#w1-sunxi #w1-gpio #w1-therm #sunxi-cir"
MODULES_NEXT=""
CPUMIN=240000

4
config/boards/nanopim1plus.conf
View File

@ -1,8 +1,8 @@
# H3 quad core 1GB SoC GbE/WiFi/BT eMMC
BOARD_NAME="NanoPi M1 Plus"
LINUXFAMILY=sun8i
BOOTCONFIG=FriendlyARM_NanoPi_M1_Plus_defconfig
MODULES="#gpio-sunxi #w1-sunxi #w1-gpio #w1-therm #sunxi-cir hci_uart rfcomm hidp dhd"
BOOTCONFIG="nanopi_m1plus_defconfig"
MODULES="#w1-sunxi #w1-gpio #w1-therm #sunxi-cir hci_uart rfcomm hidp dhd"
MODULES_NEXT="brcmfmac"
CPUMIN=240000
CPUMAX=1200000

2
config/boards/nanopineo.conf
View File

@ -1,7 +1,7 @@
# H3 quad core 256/512MB SoC Headless
BOARD_NAME="NanoPi Neo"
LINUXFAMILY=sun8i
BOOTCONFIG=FriendlyARM_NanoPi_NEO_defconfig
BOOTCONFIG="nanopi_neo_defconfig"
MODULES="#w1-sunxi #w1-gpio #w1-therm #sunxi-cir"
MODULES_NEXT=""
CPUMIN=240000

0
patch/u-boot/u-boot-sunxi/a10_a20_dram-clk.patch → patch/u-boot/u-boot-sunxi/a10-a20-lower-dram-clk.patch
View File

21
patch/u-boot/u-boot-sunxi/add-bpi-m2plus.patch Normal file
View File

@ -0,0 +1,21 @@
diff --git a/configs/Sinovoip_BPI_M2_plus_defconfig b/configs/Sinovoip_BPI_M2_plus_defconfig
new file mode 100644
index 0000000..e9a7ada
--- /dev/null
+++ b/configs/Sinovoip_BPI_M2_plus_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

134
patch/u-boot/u-boot-sunxi/add-missing-h3-boards.patch
View File

@ -1,134 +0,0 @@
diff --git a/configs/FriendlyARM_NanoPi_M1_defconfig b/configs/FriendlyARM_NanoPi_M1_defconfig
new file mode 100644
index 0000000..5ba9f9e
--- /dev/null
+++ b/configs/FriendlyARM_NanoPi_M1_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/FriendlyARM_NanoPi_NEO_defconfig b/configs/FriendlyARM_NanoPi_NEO_defconfig
new file mode 100644
index 0000000..4e7f0e4
--- /dev/null
+++ b/configs/FriendlyARM_NanoPi_NEO_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_CLK_FREQ=480000000
diff --git a/configs/FriendlyARM_NanoPi_NEO_defconfig b/configs/FriendlyARM_NanoPi_Air_defconfig
new file mode 100644
index 0000000..4e7f0e4
--- /dev/null
+++ b/configs/FriendlyARM_NanoPi_Air_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_CLK_FREQ=480000000
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/Sinovoip_BPI_M2_plus_defconfig b/configs/Sinovoip_BPI_M2_plus_defconfig
new file mode 100644
index 0000000..5ba9f9e
--- /dev/null
+++ b/configs/Sinovoip_BPI_M2_plus_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -15,3 +15,4 @@
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_VIDEO=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
new file mode 100755
index 0000000..a62d565
--- /dev/null
+++ b/configs/orangepi_zero_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_CLK_FREQ=480000000
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/FriendlyARM_NanoPi_M1_Plus_defconfig b/configs/FriendlyARM_NanoPi_M1_Plus_defconfig
new file mode 100644
index 0000000..5ba9f9e
--- /dev/null
+++ b/configs/FriendlyARM_NanoPi_M1_Plus_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=576
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
\ No newline at end of file

23
patch/u-boot/u-boot-sunxi/add-nanopi-air.patch Normal file
View File

@ -0,0 +1,23 @@
diff --git a/configs/nanopi_air_defconfig b/configs/nanopi_air_defconfig
new file mode 100644
index 0000000..61fe8c6
--- /dev/null
+++ b/configs/nanopi_air_defconfig
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_CLK_FREQ=480000000
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

21
patch/u-boot/u-boot-sunxi/add-nanopi-m1plus.patch Normal file
View File

@ -0,0 +1,21 @@
diff --git a/configs/nanopi_m1plus_defconfig b/configs/nanopi_m1plus_defconfig
new file mode 100644
index 0000000..22a833d
--- /dev/null
+++ b/configs/nanopi_m1plus_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=576
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

19
patch/u-boot/u-boot-sunxi/add-nanopi-neo.patch Normal file
View File

@ -0,0 +1,19 @@
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
index 5164245..4e7f0e4 100644
--- a/configs/nanopi_neo_defconfig
+++ b/configs/nanopi_neo_defconfig
@@ -4,12 +4,12 @@ CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_CLK_FREQ=480000000

9
patch/u-boot/u-boot-sunxi/add-orangepi-plus2.patch Normal file
View File

@ -0,0 +1,9 @@
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 4727aca..544e5ac 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -16,3 +16,4 @@ CONFIG_SPL=y
CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

22
patch/u-boot/u-boot-sunxi/add-orangepi-zero.patch Normal file
View File

@ -0,0 +1,22 @@
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
new file mode 100644
index 0000000..b27779e
--- /dev/null
+++ b/configs/orangepi_zero_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_SPI_SUNXI=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_CLK_FREQ=480000000

106
patch/u-boot/u-boot-sunxi/fix-h3-rev3-dram-calibration.patch.disabled
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@ -1,106 +0,0 @@
From f0b3ecefb7241c565b6400d2da11fc5c49b570ff Mon Sep 17 00:00:00 2001
From: Jens Kuske <jenskuske@gmail.com>
Date: Wed, 21 Sep 2016 16:08:43 +0200
Subject: [PATCH] sunxi: Fix H3 DRAM impedance calibration on rev. A chips
H3 seems to have a silicon bug breaking the impedance calibration.
This is currently worked around in software by multiple steps
combining the results to replace the wrong values.
Revision A chips need a different workaround, which is present in
the vendor bootloader too, but got overlooked in lack of
information and affected boards till now.
This commit adds a simplified version without correction factor,
which would be 1.00 for all known boards anyway.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
---
arch/arm/mach-sunxi/dram_sun8i_h3.c | 67 +++++++++++++++++++++++++------------
1 file changed, 46 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 2020d75..b23a46c 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -217,35 +217,60 @@ static void mctl_zq_calibration(struct dram_para *para)
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- int i;
- u16 zq_val[6];
- u8 val;
+ if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
+ (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0)
+ {
+ u32 reg_val;
- writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
-
- for (i = 0; i < 6; i++) {
- u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
-
- writel((zq << 20) | (zq << 16) | (zq << 12) |
- (zq << 8) | (zq << 4) | (zq << 0),
- &mctl_ctl->zqcr);
+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
+ CONFIG_DRAM_ZQ & 0xffff);
writel(PIR_CLRSR, &mctl_ctl->pir);
mctl_phy_init(PIR_ZCAL);
- zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
- writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
-
- writel(PIR_CLRSR, &mctl_ctl->pir);
- mctl_phy_init(PIR_ZCAL);
+ reg_val = readl(&mctl_ctl->zqdr[0]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[0]);
- val = readl(&mctl_ctl->zqdr[0]) >> 24;
- zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ reg_val = readl(&mctl_ctl->zqdr[1]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[1]);
+ writel(reg_val, &mctl_ctl->zqdr[2]);
}
+ else
+ {
+ int i;
+ u16 zq_val[6];
+ u8 val;
+
+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
+
+ for (i = 0; i < 6; i++) {
+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
- writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
- writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
- writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
+ writel((zq << 20) | (zq << 16) | (zq << 12) |
+ (zq << 8) | (zq << 4) | (zq << 0),
+ &mctl_ctl->zqcr);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ }
+
+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
+ writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
+ }
}
static void mctl_set_cr(struct dram_para *para)