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rockchip64-edge: add rkvdec2 for rk356x

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amazingfate 2024-06-26 16:21:39 +08:00 committed by Jianfeng Liu
parent e1f75f92cb
commit e1a64270fa
4 changed files with 62 additions and 0 deletions
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1
config/kernel/linux-rockchip64-edge.config
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@ -7847,6 +7847,7 @@ CONFIG_STAGING_MEDIA=y
# CONFIG_DVB_AV7110 is not set
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_ROCKCHIP_VDEC=m
CONFIG_VIDEO_ROCKCHIP_VDEC2=m
#
# StarFive media platform drivers

1
patch/kernel/archive/rockchip64-6.10/media-0001-Add-rkvdec2-Support-v3.patch Symbolic link
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@ -0,0 +1 @@
../rockchip-rk3588-6.10/0027-RK3588-Add-rkvdec2-Support-v3.patch

1
patch/kernel/archive/rockchip64-6.10/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch Symbolic link
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@ -0,0 +1 @@
../rockchip-rk3588-6.10/0028-media-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch

59
patch/kernel/archive/rockchip64-6.10/rk356x-add-rkvdec2-support.patch Normal file
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@ -0,0 +1,59 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index d8543b555..37141f416 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -449,6 +449,19 @@ usb2phy1_grf: syscon@fdca8000 {
reg = <0x0 0xfdca8000 0x0 0x8000>;
};
+ sram@fdcc0000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0xfdcc0000 0x0 0xb000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xfdcc0000 0xb000>;
+
+ vdec_sram: rkvdec-sram@0 {
+ reg = <0x0 0xb000>;
+ pool;
+ };
+ };
+
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
@@ -635,7 +648,7 @@ gpu: gpu@fde60000 {
};
vpu: video-codec@fdea0400 {
- compatible = "rockchip,rk3568-vpu";
+ compatible = "rockchip,rk3328-vpu";
reg = <0x0 0xfdea0000 0x0 0x800>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdpu";
@@ -686,6 +699,25 @@ vepu_mmu: iommu@fdee0800 {
#iommu-cells = <0>;
};
+ vdec: video-codec@fdf80200 {
+ compatible = "rockchip,rk3588-vdec";
+ reg = <0x0 0xfdf80200 0x0 0x500>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
+ <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CORE>,
+ <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_HEVC_CA>;
+ assigned-clock-rates = <297000000>, <297000000>,
+ <297000000>, <297000000>;
+ resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CA>,
+ <&cru SRST_RKVDEC_CORE>, <&cru SRST_RKVDEC_HEVC_CA>;
+ reset-names = "rst_axi", "rst_ahb", "rst_cabac",
+ "rst_core", "rst_hevc_cabac";
+ power-domains = <&power RK3568_PD_RKVDEC>;
+ sram = <&vdec_sram>;
+ };
+
sdmmc2: mmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;